The simulation of the quad redundant communication board requires the assistance of CAN bus technology

With the continuous development of electronic technology, computer application technology and EDA technology, the development of digital systems using FPGA has been widely used in the fields of communications, aerospace, medical electronics, industrial control, etc. FPGA has become one of the preferred methods of hardware design today. PC/104 is an industrial control bus specifically defined for embedded control. It has been widely used for its unique stack structure and low power. As a mainstream field bus, the industrial control local area network CAN (Controller Area Network) bus has strong anti-interference ability, is easy to network, and has a very broad application prospect. The unique combination of PC/104 bus and CAN bus has further broadened the application field of CAN bus.

1 CAN core design based on FPGA

This design uses Altera's Cyclone III series FPGA EP3C25, and the development platform uses Altera's Quartus II software. The design of the CAN core is based on the SJA1000 functional structure.

The functional block diagram of the CAN core is shown in Figure 1. The CAN bus controller IP core complies with the CANbus 2.0 standard, and its functions and register operations are compatible with SJA1000. The IP core is coded in VHDL and adopts a fault-tolerant design, which can suppress the data bit flipping of the storage device, greatly improving the reliability of the IP core. The CAN core can be implemented in FPGA or as ASIC. It contains three main modules: register group (can_registers), bit timing logic (can_btl), and bit stream processor (can_bsp).

Register group (CAN Register): The external microprocessor can directly access these registers through the address. When sending data, the microprocessor writes the data to be sent into the send buffer and sets the send request bit of the command register to start sending. After receiving the data, the core controller stores it in the receive buffer and notifies the bit controller to take it away. At the same time, there is a 64-byte receive FIFO in the CAN register, which can store at least 2 data frames at a time.

Bit timing logic (BTL): used to monitor the CAN bus and process the bit timing related to the CAN bus. At the beginning of the message, when the bit timing logic detects a transition from recessive to dominant on the bus, it will synchronize its internal logic to the bit stream, which is called hard synchronization; then, in the process of receiving the message, when a transition from recessive to dominant is detected, it will resynchronize to the bit stream, which is called soft synchronization. The bit timing logic also determines the position of each bit cycle sampling point based on the values ​​of bus timing register 0 and bus timing register 1 to compensate for the errors caused by transmission delay and phase drift; at the same time, the corresponding sampling mode (single sampling or 3 times) is adopted according to the setting of bus timing register 1 to sample the data on the bus.

Bit stream processor (BSP): It is divided into three modules according to the functions it implements: data receiving module, data sending module and error handling module. The data receiving module removes the bit padding from the sampled data sent from the bit timing logic and sends it to the shift register for serial-to-parallel conversion. After that, it performs CRC check on the parallel data and sends a response signal when the message is received, indicating that the reception is correct. Finally, the feature code of the received message is compared with the content of the acceptance mask register to decide whether to write the received message into the receiving FIFO. The data receiving module frames the data to be sent and performs CRC calculation, then sends it to the shift register for parallel-to-serial conversion, and then encodes the serial data (bit padding) and sends it to the bus. The error monitoring module detects system errors according to the error monitoring mechanism described in the protocol specification, sets the corresponding registers, and notifies the device controller. The module adds, subtracts, or clears the counters as appropriate according to the 12 error monitoring rules described in the protocol. The controller determines its fault state based on the values ​​of the two counters and the value of the error limit register: error active, error passire, or bus off. 2 Hardware circuit design

According to the overall design of the system, the maximum operating frequency of the existing CAN bus transceiver is 1 MHz. After the communication speed of CAN is increased, the existing CAN bus transceiver can no longer meet the needs, so the RS485 transceiver is used instead. Since the RS485 transceiver is differential transmission, it cannot complete the self-transmitting and self-receiving functions of the communication card, so an external CAN Hub is required. In addition, an external Hub is also required to perform optical fiber transmission and complete the optical logic bus structure. Therefore, this hardware design is divided into two parts: the design of the CAN communication board and the design of the CAN Hub.

(1) CAN communication board hardware circuit design

The core device of the CAN communication board is FPGA, which completes "dual-optical and dual-electrical" communication at the same time. The structure of the hardware communication board is shown in Figure 2.

As a module of the PC/104 system, it needs to be connected to the PC/104 bus, so the data, address and control bus must be consistent with the bus standards specified by the PC/104 standard.

This design requires a quad-redundant design, adding four CAN cores to the design, and using Altera's Cyclone II series FPGA EP3C25.

Since the operating voltage of PC/104 is 5 V and the operating voltage of FPGA is 3.3 V, a level converter 74LVC245 is added between PC/104 and FPGA to protect FPGA.

(2) Optical transceiver circuit

The high-speed optical transmitter of this system adopts HFBR-1414 low-power high-speed optical transmitter, and its optical emission wavelength is 820 nm. This transmitter can be used with the following four types of optical fibers: 50/125 μm, 62.5/125 μm, 100/140 μm, and 200 μm (HCS). HFBR-1414 adopts a double-lens optical system with high optical emission efficiency. When the driving current is 60 mA, an optical power of -15 dBm can be obtained on 50/125 μm optical fiber. The optical receiver adopts HFBR-2412, which integrates a photodiode, a DC circuit, and an open-collector Schottky transistor. The HFBR-2412 optical receiver can be used with the optical transmitter HFBR-1414 and 50/125 μm, 62.5/125 μm, 100/140 μm, and 200 μm (HCS) optical fibers, and the maximum communication rate can reach 5 MB. Since the open collector circuit is adopted, the receiver is compatible with TTL and CMOS levels. The communication distance of this circuit can reach up to 1.7 km.

In order to improve the comprehensive performance of the CAN communication board, such as anti-vibration and anti-interference, a double-sided wiring design is adopted. The size specifications of the communication board are strictly in accordance with the requirements of the PC/104 board.

(3) Redundancy design and CAN Hub design

The communication board is designed with 4-way redundancy. When working, only one CAN channel is working. The working channel is selected by high-bit chip select. The chip select module is designed inside the FPGA.

(4) Design of GAN Hub

Since this system adopts a "dual optical and dual electrical" quad-redundant circuit design, in order to increase the communication speed, a 485 transceiver is used instead of a standard CAN transceiver. Optical is a "point-to-point" transmission, and the 485 transceiver is a differential transmission, which cannot form a bus structure in form. Therefore, the CAN Hub is introduced to process the signal and achieve a bus structure in logic.

3 Software Design

The normal operation of the CAN communication board is inseparable from powerful software support. The core of the control part of this system adopts the PC/104 embedded computer system. The PC/104 embedded computer has powerful functions comparable to those of a PC. The development and design of the CAN communication board software part is completed on the PC/104 computer and is designed using the C language. The C language is versatile, efficient and real-time, and can meet the real-time requirements of the instrument. In the design process, a modular and structured design method is adopted to divide the software into several modules according to function. These modules have both certain independence and certain connections. The compilation requirements of each module are relatively independent, so that each module can be tested, debugged, modified and maintained. This framework mode program can ensure good versatility, maintainability, scalability, portability, interchangeability and independence.

Since the internal structure of the CAN core is the same as that of the SJA1000, the development is just like facing the SJA1000, which is simple and convenient to write. This design uses interrupt processing to process tasks. Just perform corresponding processing after the interrupt arrives.

The communication board initialization process is shown in Figure 3. The data sending process is shown in Figure 4, and the data receiving process is shown in Figure 5.

4 System Simulation

Modelsim is used for simulation .

The system testbench (TestBench) instantiates the module can4core and a CAN core cantop, and simulates the communication between them.

This simulation is carried out completely in accordance with the normal working process of the CAN core. The simulation process is as follows:

① Initialization settings. First, set the time register and data format.  Set the system design module and CAN core through the platform.

② Synchronization test. This includes hard synchronization test and resynchronization test. After a hard synchronization, the internal bit time restarts with the synchronization segment. Hard synchronization makes the jump edge that causes hard synchronization be within the restarted bit time synchronization segment.

③ Empty FIFO test (test_empty_fifo_ext). This test receives two data frames, reads the receive buffer, then clears the buffer, and reads the buffer again, repeatedly clearing and reading to see if the data in the FIFO is completely cleared.

④ Full FIFO test (test_full_fifo_ext): First clear the register, then fill the FIFO by continuously receiving data frames and read the information to check whether it can work normally.

⑤ Bus-off-test: By continuously sending data to keep the bus busy, causing bus errors, testing whether the interrupt register can detect the error, and whether the CAN core can continue to work normally after the error is cleared.

⑥Basic CAN mode sending frame detection. Test whether the CAN core can send frames normally.

⑦ Register test: By continuously reading and writing registers, check whether the CAN core registers are working properly.

⑧ Data transmission on the bus. An important point in the simulation process is whether the data information can be transmitted normally on the bus.

After simulation, we can see that the CAN communication board has broken through the speed limitation of SJA1000, the transmission speed can reach 2MHz, the effective transmission rate has been greatly improved, and the working performance is good.

Conclusion

The CAN bus communication board designed in this paper completes the communication conversion between PC/104 and CAN bus, changing the traditional design method of applying CAN controller plus external controller. On the basis of designing CAN core, all digital signal processing parts in the communication board are implemented inside FPGA, which greatly improves the communication speed. Whether in terms of transmission rate or anti-interference and anti-vibration, the comprehensive performance of CAN core application has been greatly improved.