How to Speed ​​Up Power Integrity Analysis and Signoff by 10X?

　　Introduction

　　To meet the various requirements of mobile computing, the design of system-on-chip has become increasingly complex. As consumers begin to favor smaller devices with better performance and longer battery life, the chips used in the devices must provide richer functions, lower power consumption and smaller size. For design engineers, these changes mean that they must use advanced power technology (such as power control switches), increase the content and functions of intellectual property (such as analog/mixed signal macros) and reduce design margins (such as power supply voltage less than 1V) during the design process. On the other hand, product launch cycles are getting shorter and shorter, so power sign-off is crucial to successfully submitting the design to manufacturing at the end of the design cycle.

　　Until now, available power signoff technologies have not kept pace with innovation. For example, additional runtime has been a bottleneck that has prevented designers from fully and comprehensively performing power integrity analysis and optimization. However, a new tool is now available to address this problem, leveraging advanced massively parallel algorithms and a hierarchical structure to speed up power integrity analysis and signoff by up to 10 times while achieving SPICE-like accuracy. In addition, as part of a complete flow from chip to system, the tool accelerates the design closure process by increasing productivity throughout the design cycle.

　　Increasingly complex product designs require new tools for power integrity analysis

　　The increasing complexity of product designs, shrinking product size, and increasingly complex product analysis requirements are increasing the time required to complete power integrity analysis and signoff. Using a “flat” design approach that flattens the design into a high-level layer is insufficient for analyzing very large designs with hundreds of millions of instances. Current solutions tend to partition design analysis into multiple parts that correspond to “point tools” that do not provide the accuracy or ease of use required for advanced systems-on-chip.

　　In addition, since the current solution uses single-point tools, it is impossible to effectively evaluate the impact of power on timing convergence, while timing is most sensitive to power (VDD). In addition, advanced node design technologies and techniques (such as FinFET processes and three-dimensional chip (3D-IC) packaging) also bring new challenges. For example, with the deployment of FinFET devices, new electromigration rules will be generated due to factors such as vertical current direction and increased power density. And with the deployment of three-dimensional stacked chips, there will be new needs for electrical and thermal co-simulation. In order for design engineers to meet the requirements of time to market and product quality, a complete power integrity analysis solution covering chips, packages and systems is required.

　　What does the perfect power integrity analysis tool look like?

　　A design can fail when leakage increases, temperature changes, or operating voltage drops due to static and dynamic IR drop. Whether for multi-million gate designs or multiple die, being able to debug and verify compliance with power and IR drop constraints early in the design process is key to saving valuable development cost and time. In other words, finding “hot spots” on the chip early can help prevent chip performance degradation (Figure 1).

　　To better support advanced SoC design, a perfect power integrity analysis tool should have the following features:

　　● Ability to calculate leakage on chip as well as switching and internal energy consumption;

　　● Ability to analyze the power integrity of the power network (IR drop detection and electromigration detection);

　　● Provide recommendations on the best size and placement of decoupling capacitors and power control switches in the circuit, thereby optimizing the physical implementation current of the design;

　　● Ability to evaluate the impact of IR drop on design closure including static timing analysis.

　　Cadence has developed a new power integrity analysis tool (Voltus IC Power Integrity Analysis Solution) that covers the entire chip and all cells on the chip, using algorithms and engines that have been proven in production and have sign-off quality. This tool provides all of the above functions. Its analysis speed is 10 times faster than other similar solutions, while also providing SPICE-like accuracy. In addition, the performance of this tool has been verified by Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) using 16nm FinFET processes. Therefore, engineers can be confident that the tool can provide accurate analysis results across different design rules. Massive parallel processing speeds up analysis

　　Compared with other existing technologies, the Voltus integrated circuit power integrity analysis solution has improved performance, accuracy and design convergence. In terms of performance, the tool uses advanced massively parallel algorithms to make the analysis 10 times faster than similar solutions.

　　To further demonstrate the fast analysis performance of this tool, the following is an example of a large-scale design scenario with hundreds of millions of instances at an advanced process node provided by an early beta customer. When analyzing such a large-scale design, if the existing production process is used, the hierarchical static and dynamic power sign-off takes about 10 days to complete; if the Voltus integrated circuit power integrity analysis solution is used, the analysis operation can be performed simultaneously on 32 CPUs, and the analysis work can be completed in just 26 hours - the speed is about 10 times faster than before, so the design can be sent to manufacturing in advance (Figure 2).

　　Let's look at a static power analysis case, in which an analog/mixed signal chip with 27 million instances at a 40nm node is used. If the existing production process is used, it will take 58 hours to complete the analysis. However, if the Voltus integrated circuit power integrity analysis solution is used, the analysis operation can be performed simultaneously on 8 CPUs, and it only takes 6 hours to complete the analysis work, which is about 10 times faster and does not reduce accuracy.

　　The tool uses a hierarchical structure and has excellent analysis performance. It can be calculated through a computer network and has a very large capacity (up to 1 billion instances). For example, if a single machine is equipped with 16 CPUs, the Voltus integrated circuit power integrity analysis solution can perform analysis operations on these CPUs simultaneously. If there are more than one single machine, each with multiple CPUs, and these single machines are connected to form a network, the tool can still use its multi-threaded distributed processing technology to support fast power analysis calculations. Through a hierarchical approach, engineers can build a power network model, which is a lower-level part of the design hierarchy, in order to obtain the power network information of interest. This model reduces the total number of nodes seen from the top level, so engineers can run more design instances during the analysis process compared to similar solutions (Figure 3).

　　In terms of design convergence, the Voltus tool analyzes power rails in the early low-level planning and power planning stages to physically optimize the power network through routing layout, engineering change orders (ECOs), and chip and system co-design analysis. In terms of accuracy, the Voltus integrated circuit power integrity analysis solution uses SPICE-level rail matrix solution algorithms and accurate power network resistance and capacitance extraction and instance power calculation/distribution. The rail matrix solution algorithm is relatively complex and can be performed simultaneously on dozens of CPUs distributed on multiple devices, providing high-accuracy simulation of large power networks.

　　Part of the overall sign-off process

　　The Voltus IC power integrity analysis solution is part of the entire signoff and design closure flow provided by Cadence. The tool functions similarly to an independent power signoff tool. However, it integrates many other components to provide design engineers with a prolific and fast design closure flow from chip to system.

　　Early Power Rail Analysis

　　In the traditional design flow, engineers perform power sign-off analysis after routing to evaluate the feasibility of the power network design. However, if the power integrity of the design is analyzed after routing and problems are found after analysis, it will take longer to solve the problem or may not be solved. The Voltus integrated circuit power integrity analysis solution can avoid the above problems because it is also integrated with the Cadence Encounter digital implementation system, allowing design engineers to move the power network design to the early stages of physical implementation. Early power rail analysis takes into account the bottom-level planning information, as well as the size and location of the power network metal elements. If engineers must put two functional blocks together (and both blocks are very active), the integrated solution can provide guidance on how to achieve the best routing. Good early rail analysis results will promote power sign-off and converge faster, thereby accelerating design convergence. Peak power analysis in a real environment

　　If power integrity issues like IR drop and electromigration are not addressed, they can lead to silicon failure. The accuracy of the analysis results can be improved by performing electrical stimulus analysis in a realistic environment, especially when considering the behavior of the chip over a long period of time and observing where the peak power consumption occurs under increased activity.

　　The “deep cycle” dynamic power analysis (DPA) capability provided by Cadence’s Palladium platform supports electrical stimulation analysis in a real-world environment. Thanks to this, the combination of Cadence Palladium simulation technology and the Voltus solution enables highly accurate integrated circuit power integrity analysis (Figure 4).

　　Unified electronic signature

　　Timing is most sensitive to power. Therefore, the lack of accurate and effective power values ​​in the power network instance will trigger the design protection band, which will increase the negative factors in static timing. Since the Voltus integrated circuit power integrity analysis solution is integrated with the Cadence Tempus timing sign-off solution, design engineers can use a unified power and timing analysis convergence system. The integrated solution improves the accuracy of static timing analysis by 3 percentage points, reduces the negative factors in timing, and generates a voltage drop on the chip that is more in line with the actual use environment.

　　Chip-Package-PCB Co-Simulation and Analysis

　　To prevent thermal collapse during packaging and other power integrity issues on the chip and at the printed circuit board stage, the tool integrates Cadence Allegro Sigrity technology to provide chip-package-printed circuit board co-simulation and analysis capabilities. This integrated solution provides accurate analysis of chips and boards in the power network, while also supporting advanced packaging technologies such as three-dimensional chips. By using these tools together, engineers can speed up system-level power integrity analysis and sign-off (Figure 5).

　　Summarize

　　More complex and time-consuming power integrity analysis requires more efficient analysis tools. The demand for mobile applications and IoT applications has put higher demands on product launch cycles and performance. By using advanced large-scale parallel algorithms, large-capacity analysis (supporting up to 1 billion instances) and hierarchical structures, the Voltus integrated circuit power integrity analysis solution is 10 times faster than similar solutions in terms of power signoff speed. The solution integrates other key timing analysis, physical implementation, simulation and packaging tools to form a signoff ecosystem that provides the industry with the fastest design convergence process.