Posted and Non-posted PCIE communication debugging between ARM and DSP

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Posted and Non-posted PCIE communication debugging between ARM and DSP [Copy link]

Speaking of PCIE transmission, we have to mention the two transmission modes of PCIE, posted and non-posted, which are introduced in detail in section 17.2.2 of sprugx7b.pdf.

It can be seen that Memory Read is a non-posted mode, and Memory Write is a posted mode. For the specific meanings of the two modes, please refer to the following description (source network). The PCI bus specifies two types of data transmission modes, namely posted and non-posted data transmission modes. Among them, the bus transaction using the posted data transmission mode is also called a posted bus transaction; and the bus transaction using the non-posted data transmission mode is also called a non-posted bus transaction. Among them, Posted bus transaction refers to the data transfer from PCI master device to PCI target device. When the data reaches PCI bridge, PCI bridge takes over the bus transaction from upstream bus and forwards it to downstream bus. With this data transfer mode, PCI bus can end the current bus transaction before the data reaches the final destination, thus solving the congestion of PCI bus to a certain extent. Non-Posted bus transaction refers to the data transfer mode when PCI master device transfers data to PCI target device. The data must reach the final destination before the current bus transaction can be ended. Obviously, with Posted transfer mode, when this Posted bus transaction passes through a certain PCI bus, the resources of PCI bus can be released; while with Non-Posted transfer mode, PCI bus must wait before ending the current bus transaction. This waiting will seriously block other data transmissions on the current PCI bus, so the PCI bus uses Delayed bus transactions to process Non-Posted data requests. Using Delayed bus transactions can relatively alleviate PCI bus congestion. After passing through the PCI bus, the Posted data request will release bus resources step by step, so the utilization rate of the PCI bus is relatively high. The processing process of data transmission using the Non-Posted method is different from this. When Non-Posted data requests pass through the PCI bus, bus resources will not be released in time, which will affect the utilization efficiency and transmission bandwidth of the PCI bus to some extent.