Power Management for Computer Peripherals

　　Standardization requirements

　　When you expand the functionality of a computer by adding peripherals, you need to use standard interfaces to realize the full functionality of different vendors' applications. Using wireless communications to increase the functionality of a desktop computer or increasing the memory of a laptop by using more memory sticks makes it possible to upgrade low-priced entry-level computers or add or subtract as needed. In the early 1990s, the emergence of standards for PC add-in cards made it possible to use memory sticks from different vendors in laptops.

　　PCMCIA (Personal Computer Memory Card International Association) was established to standardize the interface, allowing the use of plug-in add-on cards such as flash memory or hard drives to expand the memory of laptop computers. Many other manufacturers naturally soon realized that their specialized functions could also be added to these devices via PCMCIA cards. 　　3 Boost Converter Principle

　　The boost converter is also called a parallel switching converter in principle. The boost circuit topology is shown in Figure 2. It consists of a switch tube VT, a freewheeling diode VD, an energy storage inductor L, and a filter capacitor C. The operating frequency of the switch tube is tens to hundreds of kilohertz. It is turned on during the Ton period and turned off during the Toff period. The working cycle T=Ton+Toff. When VT is turned on, L stores energy, VD is reverse biased and cut off, and C supplies energy to the load; when VT is cut off, since the current on L cannot change suddenly, the induced potential in L causes VD to turn on to charge the capacitor and provide energy to the load at the same time. By controlling the switching frequency and the on-duty ratio, different output voltages can be obtained.

　　4 UC2843 controller introduction

　　UC2843 is a high-performance single-ended output current-mode PWM control chip with an operating temperature of -25 to +85°C and a maximum operating frequency of 500 kHz. Its biggest advantage is that it has very few external components and is very easy to assemble the external circuit. The current control loop consists of a PWM latch, a current detection comparator, an error amplifier, and a sawtooth wave oscillation circuit. It has two packages, 8 pins and 14 pins. Its internal structure is shown in Figure 3. The chip can generate a drive signal with a fixed frequency and adjustable pulse width. The oscillation frequency can be set with external components RT and CT, and the duty cycle can be accurately controlled. The output voltage can be adjusted by controlling the on-off state of the switch tube to achieve the purpose of voltage regulation.

　　UC2843 is equipped with an undervoltage lockout circuit, whose start voltage is 8.4 V and the shutdown threshold is 7.6 V. The power supply of UC2843 can be directly provided by the input voltage Ui. The start-up and shutdown difference voltage of 0.8 V can effectively prevent the circuit from oscillating when working near the threshold voltage. A 34 V Zener tube is set at the input end of UC2843 to ensure that its internal circuit works absolutely below 34 V to prevent damage caused by high voltage.

　　The OUTPUT port of UC2843 is a totem pole output. The average current output to the switch tube is +200 mA, the maximum peak current can reach ±1 A, the output low level voltage is 1.5 V, and the output high level voltage is 13.5 V, so it is suitable for driving transistors or MOSFET tubes. UC2843 is equipped with a PWM latch to ensure that only a single control pulse appears at the output end in each oscillation cycle to prevent noise interference and excessive power consumption of the power tube.

　　Manufacturers of storage, communications and gaming applications joined PCMCIA to understand or influence the interface standard so that their devices could be used in laptops. As host systems and card applications diversified, designers soon discovered that they needed to carefully consider the card's operating and startup power requirements to prevent power and system failures. For example, disk drive motor startup or power hold-up capacitors required by many applications are a potential problem. They can cause large inrush currents that overload the host power supply, causing system crashes or exceeding the safe operating area (SOA) of the host power MOSFET power switch. Issues that the PCMCIA standards committee needed to address included voltage, current (including inrush current) and sequencing. Although PCMCIA has long been disbanded, its standardized power supply specifications are still used in various other add-in cards, including PC Cards that replaced PCMCIA cards.

　　System Design Methodology

　　Similar to PC Cards, PCI Express (PCIe) addresses the power requirements of add-on cards in PCs. The same power supply considerations apply, and like PC Cards, PCIe cards can also generate secondary voltages that require sequencing and monitoring depending on the application. In addition, peripherals are still required to prevent inrush currents, and the input capacitors are cycled, which is equivalent to adding and removing

　　Power management has evolved from MOSFET switches implemented by discrete logic circuits and ASIC controllers to control one or two voltages to ASSPs such as hot-swap/soft-start controllers, power sequencers and trackers, voltage supervisors, reset generators, and watchdog timers. However, comprehensive power management design can be expensive and complex, with different applications requiring different combinations and versions of ASSPs. With hundreds of devices available from many different vendors, choosing the right combination can be a daunting task. As a result, designers often simplify their power management designs by ignoring certain possible fault conditions or assuming that a certain sequence will always occur. As an example, a power management design monitors only the input supply voltage and then powers up the other secondary voltages by enabling the next regulator when one regulator is good. To be sure, this approach reduces cost and complexity by not requiring a separate sequencer and multiple high-precision voltage monitors to monitor each voltage. However, while this sequential approach to powering up reduces cost and complexity, the response time to a power failure can be significantly delayed, which can result in severe data corruption, incomplete data packets, and the destruction of stored data.

　　　　PCIe defines voltages, currents, and card input capacitance for various slots. Figure 1 shows the PCIe specification, which defines +12 V and 3.3 V supplies and tolerances, capacitive loads, and maximum currents, including inrush currents for different cards. PCIe also supports hot-plug cards, and careful consideration needs to be given to limiting the startup voltage slew rate for hot-plug cards. Input supplies should be monitored with a voltage supervisor to determine the voltage slew rate limitations. Although PCIe does not specify power supply sequencing, a standalone application using secondary supplies may require complex sequencing.

　　Figure 2 shows the startup sequence for a PCIe card. A key parameter, shown by the arrows, is that the 12V and 3V supplies are stable within a 100ms period after the card is inserted. 100ms later, the card is enabled by the PCIe bus host by sending a PERST# high signal. Typically 100ms is too short to complete the power-up of the secondary power supplies on the card and the initialization of large FPGAs, ASICs, and other configuration devices. Pulse stretching or PERST# signal delay is often required to meet the needs of each board.

　　Figure 3 shows the power-off sequence for a PCIe card. PERST# initiates the shutdown, allowing the device to power down in a controlled manner before the supply voltage decays. If the card is suddenly removed from the slot while powered, the device will suddenly power down, which can have catastrophic consequences. Therefore, boards should be carefully designed so that they can handle sudden removals and power down the board in a controlled manner.　　There are a number of challenges to address when designing PCIe power management. For example:

　　Inrush current varies with each circuit, but there must not be any instantaneous current that exceeds the maximum PCIe supply current range. The magnitude and duration of the inrush current depends on the board's input capacitance and various other factors, such as the startup current of the FPGA or ASIC.

　　· Each card may require different plug-in controller circuitry for each application.

　　· Timing may be extended beyond the 100ms PERST# signal, delaying the reset sequence, circuit power-up, FPGA configuration circuit, and CPU reset.

　　· The device must charge fast enough so that when the power is removed the circuit will instantly shut down and the circuit board will be powered off without damaging the system.

　　All power supplies are tested for under-voltage and over-voltage conditions to protect the integrity of your operating data.

　　· The power sequence is flexible because it is unique to each application and needs to be changed as the application changes.

　　· Boards containing complex chips such as CPUs usually require a certain core circuit before I/O circuits are initialized.

　　Limitations of Discrete Design

　　How are these challenges addressed? The traditional approach to designing PCIe card power management is to use a discrete solution. Figure 4 illustrates such an approach, where the hot-swap controller, sequencer, supervisor, reset generator, and watchdog timer are all implemented separately. However, this approach has serious drawbacks. Discrete implementations require studying data sheets to select from a wide range of devices. Discrete designs are inflexible because any design change or a different application will require a different combination of discrete components. Timing and control circuits rely on R/C networks, and their timing will change as components, age, and supply voltages change. Finally, discrete designs are slow to respond to fault conditions such as accidental unplugging due to interoperability issues between devices from multiple vendors.

　　　　Integrated Solutions

　　电源管理集成到一个系统能显著降低成本，不仅可以提供所有电源管理功能，而且避免了相同功能的重复实现。共享资源的功能可以合并。例如，多个电压监控器、定序器、热插拔控制器、复位发生器集成电路和微调和裕度的功能，可以使用一块集成电路实现。一个非常精确的带隙基准可以由多种功能共享，进一步降低成本而不牺牲准确性和可靠性。更重要的是，集成将消除分立解决方案中的通信时间延迟。可以在几十微秒内实现故障响应，而不是使用微处理器监控的系统通常所需的几百毫秒。微调、裕度和电压测量可以通过添加一个 ADC 和一个 DAC 轻松实现。

　　ASICs can combine some of the discrete components needed for power management. However, they typically require some additional integrated circuits, including a microprocessor, to implement the solution and include some features that are not required for the application. In addition, ASIC-based solutions are difficult to simulate and, as a "fixed" approach, require that any changes be implemented off the board.

　　Another more efficient approach is to use a single integrated power management IC. By integrating all power management functions, several key issues of discrete solutions are resolved. The internal communication and slow response to system error conditions caused by separate devices from different vendors are alleviated: they can be processed in just a few microseconds. The overall cost is also reduced because key functions are shared by several channels.

　　For example, the Lattice POWR1014A integrates 10 programmable voltage monitors and uses a bandgap reference to achieve 0.3% voltage monitoring accuracy for all channels.

　　
Figure 5 POWR10414A structure

　　The internal clock and built-in digital timer solve the inaccuracy problems caused by devices using external R/C networks. The digital I/O, programmable timer and CPLD core monitor PERST# and PRSNT# and generate card-specific timing to ensure correct timing and configuration. Additional signals can be generated based on the inputs to notify the system of reset or brown-out conditions. The POWR1014A contains two charge pumps to control N-channel MOSFETs. The hot-swap function can be easily customized for each application by changing the gate voltage and charge rate while monitoring the system's current and voltage to ensure that PCIe limits are met. The CPLD core can easily modify the design for various applications, board and vendor changes. The inputs and outputs can be easily configured and the CPLD core programmed using Lattice's PAC-Designer design software.

　　Summarize

　　PCI Express has standardized the interface and timing between PCs and add-in cards. Various applications require custom designs for each unique current, timing, voltage, and sequencing function. Discrete solutions are expensive and lack precise timing, low accuracy, reliability issues due to the larger component materials, and flexibility issues once the design needs to be changed. Lattice's POWR1014A integrates PCIe power management into a precise, flexible, programmable and low-cost solution.