Improved interleaved DC/DC converters

　　Interleaved DC/DC converter topologies enable higher efficiency designs than conventional parallel output stage transistors, and there is still room for improvement. In interleaved operation, many tiny converter cells (or phases) are placed in parallel. Ideally, active phase-shift control circuits distribute power evenly across the phases, and this approach eliminates current ripple at the output and increases the effective ripple frequency, reducing the output filter capacitor requirements. Interleaving also significantly reduces input inductor and capacitor requirements.

　　However, this approach has several disadvantages. One is that there is a trade-off between the full-load efficiency of the converter and the light-load efficiency. With the transistor stages connected in parallel, the conduction losses are reduced, but the switching losses are increased. At full load, the conduction losses dominate and there is no problem. But at light load, the opposite is true, and switching losses dominate. In addition, current sharing between the phases is a cumbersome issue, which is generally handled by active control circuits (without which tiny device mismatches between the parallel phases can cause huge phase current imbalances), and some methods are better than others.

　　Figure 1. Two-phase interleaved two-switch forward converter.

　　Digital power management, with its ability to execute complex control algorithms and data bus capabilities, can address these issues more effectively. Below we will apply this technology to a two-phase interleaved two-switch forward converter to achieve real-time optimization.

　　Improve efficiency

　　A. The total energy loss of the light-load and heavy-load switching power converter is equal to the sum of the conduction loss PcONd and the switching loss Psw. Given the output current Iout and the switching frequency fs, the switching loss is (Formula 1):

　　Where ksw1 and ksw2 are device-dependent switching loss factors. Generally speaking, the larger the transistor size, the higher ksw1 and ksw2.

　　Ignoring the inductor current ripple, the conduction loss on the path resistance Rpath is (Formula 2):

　　Using interleaved phases in parallel can reduce the path resistance, thereby improving the heavy load efficiency. However, the power loss at light load is dominated by switching losses. As ksw1 and ksw2 increase with more phases, interleaving significantly reduces the light load efficiency. Therefore, compared with a single-phase converter, an interleaved multiphase converter has higher heavy load efficiency, but lower light load efficiency. The efficiency of the converter is (Equation 3):

　　For a single-phase converter, the power conversion efficiency is 0 at no load because the switching loss part Psw2 always exists. When the output current increases, Psw2 becomes negligible, so the efficiency increases accordingly. The denominator in Formula 3 is a second-order polynomial, while the numerator is only first-order, so when the output current passes the optimal point, the efficiency begins to decrease again.

　　For a two-phase converter, the output current at the optimum efficiency point is twice that of a single-phase converter. Therefore, more phases result in higher efficiency at heavy loads, but lower efficiency at light loads.

　　Previously, it was believed that only full-load efficiency was important. However, today, power converters are more likely to power light loads than heavy loads. With the increasing demand for energy conservation, high light-load efficiency is critical for power supplies. Therefore, designers want to use smart interleaving controllers to achieve high-efficiency operation at all loads.

　　B. Real-time optimization of efficiency by controlling the number of phases The above power loss analysis shows that it is not appropriate to have two parallel phases operating at light load at the same time. If one phase is turned off, the situation will change significantly. The conduction losses increase, but the switching losses decrease, so the light load efficiency is higher. The key is to ensure that the number of phases is optimized in real time.

　　Figure 2 shows the experimental waveforms of a two-phase interleaved two-switch forward converter, in this case controlled by the ADP1043 digital controller from Analog Devices. When the total load current drops below a certain threshold, the second phase is disabled. As shown in Figure 3, the light load efficiency is improved when one phase is turned off. The difference in light load efficiency between and without phase optimization control can be as high as 15%.

　　Figure 2. Automatic phase shutdown using the ADP1043.

　　C. Real-time efficiency optimization through DCM operation As can be seen in Figure 3, for very light loads, the efficiency drops significantly even in single-phase operation. One reason is that the converter uses synchronous rectifiers on the secondary side (Figure 1). When the output current level is lower than the current ripple, reverse current flows through the output inductor. This circulating current causes conduction losses. To improve efficiency, one solution is to turn off all secondary synchronous rectifiers and let the body diode or parallel diode (Schottky diode in most cases) handle freely. When the load is low enough, the converter operates in discontinuous current mode (DCM), thus avoiding the problem of circulating current.

　　Figure 3. High-efficiency interleaved two-switch forward converter.

　　With this scheme, the converter efficiency is 5% higher than that in continuous current mode (CCM). In addition, shutting down one phase at light load can further improve the efficiency across the entire application load range.

　　D. Other Considerations In addition to taking the above measures to optimize real-time efficiency, designers must also carefully consider the design of the power stage and controller. The power stage, sensing network, and feedback control circuit have inherent propagation delays, so during fast load step-up transients, the system must maintain the output voltage of the first phase stable before starting the second phase. Also, the system should be able to handle full power for a short period of time. Transistor selection should be based on this thermally sensitive condition. In addition, the magnetics should be designed to avoid saturation of the system at higher output currents.

　　As for the controller, the feedback compensator needs to be adjusted according to different operating modes, because the power stage transfer function will change with the number of phases and CCM/DCM conditions. This requires the controller to provide intelligent management, which is difficult for traditional controllers to do.

　　Additionally, the digital power management controller automatically detects load conditions and smoothly switches to the appropriate converter mode.

　　Phase-by-phase interleaving does not in itself ensure even current sharing. Since the paralleled phases share the same voltage feedback, there is no error due to mismatched reference voltages.

　　Therefore, load imbalance is related to device tolerance, drive imbalance, and timing errors.

　　Current imbalance causes thermal and device stress. Transistors and magnetics must be designed to protect against possible overstress conditions. In addition, efficiency is affected. For example, if the total current of an interleaved forward converter is 30A and the two phases provide 10A and 20A respectively, the efficiency drop due to this factor is close to 1%.

　　There are two control schemes that can be used to achieve current sharing among phases: inner loop current sharing and dual loop current sharing. Inner loop current sharing is essentially current mode control. The output of the voltage compensator is used as a current sharing bus to provide output current reference for all phases. Within the voltage loop, the current sharing loop design is not limited by the voltage bandwidth, and the current sharing response can even be faster than the voltage loop. However, when designing the outer voltage loop, the impact of the inner loop must be considered. If the inner loop is faster, the voltage regulation function of the outer loop may be weakened.

　　In dual-loop operation, the voltage regulation loop and the current sharing loop are connected in parallel. Each phase has a dedicated current sharing compensator to ensure that its current follows the current sharing bus, which can be the average current of the parallel phases or the highest phase current. The output of the current sharing loop of each phase is added to the common voltage compensator output to generate the duty cycle signal of that phase. In this way, both the current sharing controller and the voltage regulation controller affect the generation of the duty cycle signal. When using this control structure, each loop can be designed flexibly, and the designer does not have to worry too much about the mutual influence between the current sharing loop and the voltage regulation loop.

　　Regardless of the current sharing scheme used, the current of each phase must be sensed for active control. The traditional approach is to use a current sensing scheme for each phase. Current sensing is generally used for protection purposes, and this technique adds cost to the interleaved converter.

　　In order to sense the current of two phases with one input, the controller must separate the current of each phase. In interleaved forward operation, the duty cycle of the main switch is always less than 50% to avoid transformer saturation. With 180 degrees of phase shift, there is no signal overlap in the main switch current sensing. Therefore, digital control can distribute the sensing signal to align it with the duty cycle signal of each phase. In this way, the current of each phase can be clearly distinguished using only one current sensing circuit. The controller monitors the current flowing in each phase, stores this information, and compensates the drive signal to ensure current sharing.

　　Figure 4 shows an example of an interleaved forward converter using the ADP1043 controller to implement the above scheme. It is clear that since the duty cycle is less than 50%, the controller can determine the current of each phase using a common current sense point. Without current sharing control, the current of the second phase is almost twice that of the first phase. With current sharing control enabled, the current difference between the two phases is greatly reduced to 5%.

　　Figure 4. Effect of two-phase current sharing control

　　(Top) Current sharing control is enabled; (Bottom) Current sharing control is disabled.

　　In summary, interleaved operation offers advantages not available in single-phase designs. The benefits of interleaved operation can be further amplified using digital power management. Digital control also enables simple current sharing schemes.