MOSFET Selection for Power System Switching Controllers

MOSFET selection for DC/DC switching controllers is a complex process. Considering only the voltage and current ratings of the MOSFET is not enough to select the right MOSFET. To keep the MOSFET within the specified range, a balance must be struck between low gate charge and low on-resistance. This becomes even more complicated in multi-load power supply systems. Online design tools such as WEBENCH® Power Designer from Texas Instruments (TI) can simplify this process, allowing users to make the right choices based on efficiency, size and cost to achieve the ideal MOSFET controller design goals.

Figure 1 - Step-down synchronous switching regulator schematic

DC/DC switching power supplies are widely used in many modern electronic systems due to their high efficiency. For example, a buck synchronous switching regulator with both a high-side FET and a low-side FET is shown in Figure 1. These two FETs switch according to the duty cycle set by the controller to achieve the desired output voltage. The duty cycle equation for the buck regulator is as follows:

1) Duty cycle (high side FET) = Vout/(Vin*efficiency)

2) Duty cycle (low-side FET) = 1 – DC (high-side FET)

The FET may be integrated into the same chip as the controller, which provides the simplest solution. However, to provide high current capability and/or achieve higher efficiency, the FET needs to remain external to the controller. This allows for maximum heat dissipation because it physically isolates the FET from the controller and provides the most flexibility in FET selection. The downside is that the FET selection process is more complex because there are many factors to consider.

A common question is “Why won’t this 10A FET also work for my 10A design?” The answer is that this 10A current rating is not appropriate for all designs. Factors to consider when selecting a FET include voltage rating, ambient temperature, switching frequency, controller drive capability, and heat sink area. The key issue is that if the power dissipation is too high and the heat sink is insufficient, the FET may overheat and catch fire. We can estimate the junction temperature of a FET using the package/heat sink component ThetaJA or thermistor, the FET power dissipation, and the ambient temperature as follows:

3) Tj = ThetaJA * FET power dissipation (PdissFET) + ambient temperature (Tambient) It requires the calculation of the power dissipation of the FET. This power dissipation can be divided into two main parts: AC and DC losses. These losses can be calculated using the following equations:

4) AC Losses: AC power consumption (PswAC) = ½ * Vds * Ids * (trise + tfall)/Tsw Where Vds is the input voltage of the high-side FET, Ids is the load current, trise and tfall are the rise and fall times of the FET, and Tsw is the switching time of the controller (1/switching frequency).

5) DC loss: PswDC = RdsOn * Iout * Iout * Duty cycle

Where RdsOn is the on-resistance of the FET and Iout is the load current for the buck topology.

Other losses come from output parasitic capacitance, gate losses, and body diode losses from conduction during the low-side FET dead time, but in this article we will focus on AC and DC losses.

AC switching losses occur during the transition between the switch turning on and off when both the switch voltage and current are non-zero. This is shown in the highlighted portion of Figure 2. According to Equation 4), one way to reduce these losses is to shorten the rise and fall times of the switch. This can be achieved by selecting a FET with a lower gate charge. Another factor is the switching frequency. The higher the switching frequency, the greater the percentage of the switching time is spent in the rise and fall transition region shown in Figure 3. Therefore, higher frequency means greater AC switching losses. Therefore, another way to reduce AC losses is to reduce the switching frequency, but this requires larger and usually more expensive inductors to ensure that the peak switch current does not exceed the specification.

Figure 2 - AC loss diagram

Figure 3 - Effect of switching frequency on AC losses

DC losses occur when the switch is in the on state due to the on-resistance of the FET. This is a fairly simple I2R loss mechanism, as shown in Figure 4. However, the on-resistance varies with the FET junction temperature, which complicates the situation. Therefore, an iterative approach must be used to accurately calculate the on-resistance using equations 3), 4), and 5), taking into account the temperature rise of the FET. The simplest way to reduce DC losses is to select a FET with a low on-resistance. In addition, the amount of DC losses is directly proportional to the percentage on-time of the FET, which is the high-side FET controller duty cycle plus 1 minus the low-side FET duty cycle, as described previously. From Figure 5, we can see that longer on-time means more DC switching losses, so DC losses can be reduced by reducing the on-time/FET duty cycle. For example, if an intermediate DC voltage rail is used and the input voltage can be modified, the designer may be able to modify the duty cycle.

Figure 4 - DC loss diagram

Figure 5 - Effect of duty cycle on DC losses

Although choosing a FET with low gate charge and low on-resistance is a simple solution, there are trade-offs and balances between these two parameters, as shown in Figure 6. Low gate charge generally means smaller gate area/fewer parallel transistors, and thus higher on-resistance. On the other hand, using larger/more parallel transistors generally results in low on-resistance, which results in more gate charge. This means that FET selection must balance these two conflicting specifications. In addition, cost factors must also be considered.

Figure 6 - Comparison of on-resistance and gate charge for some new FETs that effectively balance these two parameters

Low duty cycle designs mean high input voltages, and for these designs, the high-side FET is mostly off, so DC losses are low. However, high FET voltages result in high AC losses, so a FET with low gate charge can be chosen, even though the on-resistance is high. The low-side FET is mostly on, but the AC losses are minimal. This is because the voltage across the low-side FET during on/off is very low due to the FET body diode. Therefore, a FET with low on-resistance needs to be chosen, and the gate charge can be high. Figure 7 shows this.

Figure 7 - High-side and low-side FET power dissipation for low duty cycle design

If we reduce the input voltage, we can get a high duty cycle design where the high-side FET is on most of the time, as shown in Figure 8. In this case, the DC losses are higher, requiring low on-resistance. Depending on the input voltage, the AC losses may not be as important as with the low-side FET, but they are still not as low as with the low-side FET. Therefore, a reasonably low gate charge is still required. This requires a compromise between low on-resistance and low gate charge. For the low-side FET, the on-time is minimized and the AC losses are lower, so we can choose the right FET based on price or size rather than on-resistance and gate charge.

Figure 8 - High-side and low-side FET power dissipation for a high duty cycle design

Assuming that we can specify a nominal input voltage for an intermediate voltage rail for a point-of-load (POL) regulator, what is the best solution, high input voltage/low duty cycle or low input voltage/high duty cycle? As an example, we create a design in TI's WEBENCH Power Designer. The duty cycle is modulated with different input voltages and the FET power dissipation is observed. The high-side FET response curve in Figure 9 shows that the AC losses decrease significantly when the duty cycle increases from 25% to 40%, while the DC losses increase linearly. Therefore, a duty cycle of about 35% should be the ideal value for choosing a FET with a balance of capacitance and on-resistance. Continuously reducing the input voltage and increasing the duty cycle can get the lowest AC losses and the highest DC losses. For this, we can use a FET with a low on-resistance and compromise with a high gate charge. As shown in Figure 10 of the low-side FET, the DC losses decrease linearly when the controller duty cycle increases from low to high (the low-side FET is on for a shorter time), and the losses are minimized at high controller duty cycles. The AC losses across the board are low, so low on-resistance FETs should be chosen in all cases.

Figure 9 - High-side FET losses vs. duty cycle

Figure 10 - Low-side FET losses vs. controller duty cycle. Note: The low-side FET duty cycle is 1-controller duty cycle, so the low-side FET on-time decreases as the controller duty cycle increases.

Figure 11 shows how the total efficiency changes when we combine the high-side and low-side losses. We can see that in this case, the combined FET losses are lowest and the efficiency is highest at high duty cycles. The efficiency increases from 94.5% to 96.5%. Unfortunately, to get low input voltages, we must step down the voltage of the intermediate voltage rail supply, increasing its duty cycle since it is powered from a fixed input supply. Therefore, this may offset some or all of the gains made at the POL. Another approach is to not use the intermediate rail and go directly from the input supply to the POL regulator in order to reduce the regulator count. In this case, the duty cycle is lower and we must be careful with the FET selection.

Figure 11 - Total losses vs. efficiency and duty cycle

The situation is more complicated in power systems with multiple output voltages and current requirements. The WEBENCH Power Designer tool can be used to visualize the trade-offs in such systems. This tool allows users to see various scenarios using different intermediate rail voltages and compare the efficiency, cost, and size of different POL regulator duty cycles. Figure 12 shows a system with a 28V input voltage and 8 loads with 4 different voltages ranging from 3.3V to 1.25V. There are three comparison methods: 1) no intermediate rail, 28V directly from the input supply to achieve a low duty cycle for the POL regulator; 2) using a 12V intermediate rail and a medium duty cycle for the POL regulator; 3) using a 5V intermediate rail and a high POL regulator duty cycle. Figure 13 and Table 1 show the results of the comparison. In this case, the architecture with no intermediate rail power achieves the lowest cost, the architecture with a 12V intermediate rail voltage achieves the highest efficiency, and the architecture with a 5V intermediate rail voltage achieves the smallest size. So we can see that for this large system, there is no clear trend in any of these parameters that we have seen for the single POL supply case. This is because when using multiple regulators, each regulator, in addition to the intermediate rail regulator itself, has its own different load current and voltage requirements that may conflict with each other. The best way to investigate this situation is to use a tool such as WEBENCH Power Designer to evaluate the different options.

Figure 12 - Power system showing input, intermediate rail, point-of-load (POL) supply, and load. Different choices for intermediate rail voltage are 28V (using input supply directly), 12V, and 5V. This results in different POL regulator duty cycles.

Figure 13—WEBENCH® Power Design graph showing the impact of intermediate rail voltage on power system efficiency, size, and cost. The circle diameter is the BOM (Bill of Materials) price.

Table 1 - Impact of intermediate rail voltage on power system efficiency, size and cost.

In summary, FET selection is a complex task, but if the right choice is made, a low-cost, high-efficiency power system can be achieved. Tools such as WEBENCH Power Design can help users visually compare different approaches, make trade-offs, and balance choices, so as to quickly obtain an ideal design.

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Visit  http://www.national.com to get the WEBENCH Power Designer tool using the multiple output voltage options of the WEBENCH panel.

Resume:

Jeff Perry is the senior development manager for TI's WEBENCH online design environment. He graduated from UCLA with a Bachelor of Science in Physics and received an MBA from San Jose State University. He started out in semiconductor technology before moving into power applications and development. He has been involved in the development of WEBENCH since its initial release in 1999. Jeff Perry holds 12 patents.