Design and production of dynamic scanning digital clock circuit

In the electronic technology experimental teaching, the fundamental purpose and core content of teaching are to build circuit design concepts and improve circuit design capabilities. The design of digital clock circuits includes sequential logic circuits, combinational logic circuits, digital tube display circuits and pulse signal generation circuits. The content covers a wide range and is highly comprehensive. It is a typical case of autonomous experimental teaching of electronic technology. This paper uses quartz crystal oscillator circuits, counting circuits, dynamic scanning and decoding drive circuits, display circuits and clock correction circuits to realize the circuit.

1 System Design

The digital clock designed this time can realize the digital display of hours, minutes and seconds, with a cycle of 24 hours, a full scale of 23 hours, 59 minutes and 59 seconds, and has the function of time calibration. The circuit mainly adopts medium-scale CMOS integrated circuits, uses batteries as power supply, and displays the clock through common cathode LED digital tubes. The system consists of a second pulse generation module, a counter module, a decoding display circuit module, a dynamic scanning module, and a time calibration module. The second pulse generation module consists of a crystal oscillator circuit and two frequency divider circuits, and the dynamic scanning module consists of three parts: a dynamic scanning control signal generation circuit, a counter gating control circuit, and a digital tube gating control circuit. The system composition block diagram is shown in Figure 1.

1.1 second pulse generation circuit

The second pulse signal is generated by a quartz crystal oscillator. Since the output frequency of the crystal oscillator is relatively high, in order to obtain a 1 Hz second signal, the output signal of the oscillator needs to be divided. The usual frequency divider is implemented using a multi-level binary counter. The 32 768 Hz high-frequency square wave signal is divided 32 768 (215) times to obtain a 1 Hz square wave signal for the second counter to count. That is, the counter that realizes this frequency division function is equivalent to a 15-level binary counter.

This design uses CD4060 to form a 14-level 2-frequency division circuit.

Pin 9, 10 and 11 of CD4060 contain two NOT gate circuits. Pin 1 outputs 12-frequency division signal, pin 2 outputs 13-frequency division signal and pin 3 outputs 14-frequency division signal. The two NOT gates of CD4060 and the 32768Hz crystal oscillator form a 32768Hz oscillator, and then the CD4060 performs 214 division to obtain a 2Hz signal, and then the D flip-flop CD4013 performs a 2-division to obtain a 1Hz second pulse. The circuit diagram is shown in Figure 2.

1.2 Counter Design

The counter circuit is used to complete the counting of 60 seconds, 60 minutes and 24 hours, and the carry pulse of the second counter is used as the input pulse of the minute counter, and similarly, the carry pulse of the minute counter is used as the input pulse of the hour counter. The "second", "minute" and "hour" counter circuits are completed using the synchronous add counter CD4518.

(1) CD4518 Dual BCD Synchronous Adding Counter

CD4518 is a dual BCD decimal counter. It contains 2 independent counting units, 2 counting pulse input terminals, rising edge trigger terminal CP and falling edge trigger terminal EN. If CP is used to trigger, EN is connected to a high level and is a rising edge trigger; if EN is used to trigger, CP is connected to a low level and is a falling edge trigger; there are 4 output terminals QD~QA and a reset terminal.

The pin diagram of CD4511 is shown in Figure 3. Among them:

CP: Clock input terminal, rising edge triggered;

EN: Clock input terminal, falling edge triggered;

R: reset terminal, when high level, counter = 0;

QD~QA: count value decimal output terminal;

UDD: positive power input terminal (3~15 V);

USS: power reference ground.

(2) Design of “hour”, “minute” and “second” counters

The two decimal counters inside CD4518 are cascaded to form a 100-base counter, and then a 60-base counter is realized through the feedback method. The circuit is shown in Figure 4. In the figure, QD1, QC1, QB1, QA1 are the binary BCD codes of the second digit, and QD2, QC2, QB2, QA2 are the hexadecimal BCD codes of the second digit. When the digit is to display decimal 6, that is, 0110, QC2 and QB2 are both 1 at this time, and the output through CD4081 (42-input AND gate) is also high level, and low level at other times. This pulse signal is used to clear the tens counter, and this pulse signal is also the input signal of the pulse division.

The minute counter circuit is exactly the same as the second counter circuit, except that the pulse input is different, the second counter is 1 Hz, while the minute counter is 1 60 Hz.

The hour counter is a 24-bit counter. The design principle is the same as that of the minute and second counter. The difference is that the feedback reset state is different. When the tens digit (display 2) and the ones digit are 0100 (display 4), all counters are reset. Send QB2 and QC1 to the reset end of the two decimal counters through CD4081.

1.3 Digital display and dynamic scanning circuit

The digital display uses a common cathode LED digital tube. The decoding display drive circuit uses the BCD-7 segment latch decoder/driver CD4511. There are two driving modes for multi-digit display of digital tubes: one is static driving, which is a method of continuously applying driving voltage to each display to keep the display lit. Each display must be equipped with a set of counters, decoders and drive circuits. The principle of static driving is relatively simple and is suitable for occasions with a small number of digits. When the number of digits is large, the number of components used increases and the power consumption is also large. Another method is dynamic driving. The dynamic driving method uses a scanning method to let each digital tube display in turn in a certain order. Its advantages are: first, it can reduce power consumption, which is particularly important for battery-powered portable digital instruments; second, each display shares a decoder, which saves the number of decoders and reduces wiring; third, it can output multiple BCD codes and is easy to connect to a computer. As long as the scanning frequency is high enough, the flicker phenomenon cannot be observed due to the temporary effect of the human eye.

The overall characteristics of dynamic scanning are bit scanning and segment gating drive. This design adopts dynamic scanning mode, and the dynamic drive principle diagram of two-bit LED display is shown in Figure 5.

The pulse distributor CD4022 is used to generate dynamic scanning signals DS0~DS5. Only one of these six signals is high at the same time. DS0~DS5 is used to control the analog switch CD4066. When a scanning signal is high, the four analog switches controlled are turned on, so that the data of the corresponding counter is sent to the decoding drive circuit. At the same time, the scanning signal must select the corresponding digital tube to display the corresponding data. Since a common cathode digital tube is used, the scanning signal can select the corresponding digital tube through the Darlington transistor MC1413. When a scanning signal is high, it becomes low after being output by MC1413, and the corresponding digital tube is lit. The frequency of the input pulse CP of the pulse distributor CD4022 should be high enough. Here, 512 Hz is selected (provided by the 13th foot of 4060).

1.4 Timing Circuit

Time calibration is a basic function that a digital clock should have. When the digital clock is powered on or has calibration functions such as hours, minutes, and seconds, to make the circuit simple, only the minutes and hours are calibrated here. The calibration circuit requires that the normal counting of minutes and seconds should not be affected when calibrating the hours, and the normal counting of seconds and hours should not be affected when calibrating the minutes.

There are many calibration methods, the most commonly used one is the "fast time calibration method". The original circuit diagram of the time calibration circuit is shown in Figure 6.

2 Conclusion

The design of digital clock circuit involves many aspects of knowledge such as analog electronic technology and digital electronic technology. Including it in the independent experiment content overcomes the shortcomings of the previous practical teaching form of single and simple and boring content [8]. The design is required to be completed independently during the experiment. The digital clock circuit can be made by welding a universal board, or by drawing a PCB circuit diagram and using the thermal transfer method to make a homemade PCB circuit board to complete the production of the circuit.