Design of ADC front-end matching network in ultra-wideband system

introduction

In the design of the traditional narrowband wireless receiver, DVGA+anti-aliasing filter+ADC link, we default the ADC to a high impedance state and ignore the impact of the ADC internal resistance when simulating the anti-aliasing filter. However, with the rapid development of wireless technology, the required signal bandwidth is getting wider and wider, and the corresponding signal frequency is getting higher and higher. In this case, the ADC's internal resistance that changes with frequency cannot be ignored. In order to achieve better signal in-band flatness, the design of the ADC front-end matching circuit is introduced, especially for the non-input buffer ADC in the high-load anti-aliasing filter application scenario. The design of the front-end matching circuit is even more important in ultra-wideband applications. This article will take ADS58H40 as an example to introduce the design of the ADC front-end matching circuit.

Non-input buffer ADC internal resistance characteristics and its equivalent model

The input internal resistance of an ideal ADC should be in a high impedance state, that is, the impact of the ADC internal resistance does not need to be considered in the design of the front-end anti-aliasing filter. However, the actual ADC internal resistance is not infinite and will change with frequency. From the perspective of input internal resistance, ADCs can be divided into two categories: one is an ADC with an input buffer, whose input characteristics are more like an ideal ADC and whose internal resistance is often relatively large; the other is an ADC without an input buffer, whose internal resistance cannot be ignored at high frequencies and changes with frequency, but whose power consumption is smaller than that of the former. Figure 1 shows the analog input equivalent internal resistance model of the non-input buffer ADS58H40. The impedance network equivalent to the sampling and holding circuit at the analog input of the ADC changes with frequency; coupled with the ADC sampling noise absorption circuit (glitch absorbing circuit) RCR circuit, its existence improves the SNR and SFDR of the ADC, but also makes the internal resistance of the ADC change more with frequency. The superposition of the two effects makes the equivalent load of the ADC capacitive as a whole.

Figure 1 ADS58H40 analog input equivalent internal resistance model

Figure 2 shows the curve of the internal resistance changing with frequency, taking ADS58H40 as an example. A series model, the series equivalent resistance value in the series model is in the Ohm level. B parallel model, the parallel equivalent resistance value in the parallel model is in the kOhm level at low frequencies (< 100MHz), but as the input frequency continues to increase (>200MHz), the parallel equivalent resistance value will drop sharply to the hundred ohm level, making it non-negligible relative to the load at the ADC end of the anti-aliasing filter. Moreover, regardless of the equivalent capacitance in the parallel model or the series model, the load characteristics of the anti-aliasing filter ADC end deviate from the ideal resistive characteristics and need to be compensated.

Figure 2 ADS58H40 internal resistance simplified model: A series model, B parallel model; and its related frequency variation curve

Non-input buffer ADC front-end matching network topology architecture
Since the equivalent internal resistance of the ADC changes with frequency and deviates from the ideal high impedance state at high frequencies, the selection of the load impedance of the anti-aliasing filter ADC end is particularly important. The ideal ADC supports any selection of the load of the anti-aliasing filter, without any requirements. However, the change of internal resistance makes the ADC in reality hope that the load impedance of the front-end anti-aliasing filter can be relatively small, that is, in the design of the traditional 50Ohm anti-aliasing filter, the kOhm-level internal resistance of the ADC can be ignored relative to 50Ohm. However, more and more anti-aliasing filters now require a 100Ohm load design to achieve the optimal working state of the front-end driver level. Figure 5 Taking the DVGA LMH6521 commonly used in the current wireless base station design as an example, in order to achieve the optimal linear performance of the entire receiving link, it is recommended to use a 100Ohm anti-aliasing filter. At this time, if a simple 100Ohm load is still connected in parallel to the ADC input, as the input signal frequency increases and the input signal bandwidth widens, the non-ideal characteristics of the ADC internal resistance will become more and more obvious, which will directly pull down the 100Ohm load on the ADC side and deteriorate the in-band flatness of the signal.

Figure 3 Schematic diagram of DVGA optimal working state load requirements

In order to unify the design of anti-aliasing filters to simplify their porting in different platform projects, it is hoped that the ADC side (including ADC equivalent internal resistance and front-end matching circuit) will present consistent impedance characteristics throughout the entire signal bandwidth, such as 100Ohm in the application of Figure 3. The ADC front-end matching network is introduced as shown in Figure 4.

Figure 4 Non-input buffer ADC front-end matching network topology architecture diagram

in:

1. R1 and R2 are the main components of the impedance on the ADC side. Assuming the ideal high-impedance characteristics of the ADC, it represents the load on the ADC side. Due to the limited internal resistance of the ADC and the required matching network, in order to achieve the overall effect and still maintain a 100Ohm load state, R1 and R2 are much higher than the optimal value of 50Ohm. R1 and R2 not only determine the actual common-mode voltage of the ADC input pin (VCM-Analog input common mode current*R1, the performance SNR and SFDR of the ADC will change slightly with the change of VCM, please refer to datasheet Figure 22); but also the low-resistance discharge path of the sampling glitch, so it should not be too large. The principle of selecting the value of R1 and R2 is to achieve the minimum value under the premise of achieving the combined load target on the ADC side, and the maximum value should not exceed 100Ohm.
2. R5 and R6 represent 5Ohm or 10Ohm damping resistors connected in series with the ADC input port to attenuate oscillations that may be caused by parasitic inductance of the bonding wire.
3. The network composed of R3-L1-L2-R4 is mainly responsible for adjusting the in-band flatness in ultra-wideband applications. Its existence is significant because this network is inductive and its impedance increases with frequency; it changes in the opposite direction to the ADC equivalent internal resistance that decreases with frequency, and the two parallel connections keep the overall impedance as constant as possible within the required frequency range. If you think the network is too complicated, you can also consider merging L1 and L2 into one inductor to disconnect the VCM connection; consider separating into two inductors only to provide a path for the VCM current to be parallel to R1+R2 to reduce the deviation of VCM from the ideal value.
4. The network composed of R7-L3//C1-R8 is mainly responsible for absorbing sampling glitch. In the application of 50Ohm load anti-aliasing filter, the 50Ohm load path is equivalent to the low-impedance discharge path of sampling noise, so the RL//CR circuit can generally be omitted. However, when the load impedance of the anti-aliasing filter increases, such as the application of 100Ohm anti-aliasing filter mentioned above, the RL//CR network is recommended in applications with higher performance requirements. Sampling noise is caused by the switching of the sampling switch. Only by directly introducing a low-impedance path at the ADC input pin can it be effectively absorbed, which is why the RLCR network needs to be laid out as close to the ADC input pin as possible. Otherwise, the sampling noise will be converted into noise that affects the performance of the ADC under the action of dither, thereby deteriorating the SNR and SFDR. The most important component of this sampling noise absorption circuit is the capacitor. The sampling noise is mostly composed of high-frequency components, and a low-impedance path is formed for it, that is, a low-pass circuit or a band-pass circuit (high impedance for useful signals and low impedance for high-frequency noise). The value of C should not be too small, which will affect the absorption effect. It should not be too large, which will seriously affect the input bandwidth. The R in series at both ends should not be too large. 25Ohm is appropriate. The parallel inductor mainly reduces the Q value and helps to flatten the intra-band fluctuation. When the R3-L1-L2-R4 and R7-L3//C1-R8 networks coexist, L3 needs to be removed to form an R-CR network for the consideration of intra-band flatness.

Simple value-taking steps and principles:

1. If it is a traditional 50Ohm anti-aliasing filter design, R1 and R2 are 25Ohms each, there is no need to add the RLLR network, and the RL//CR network is optional.
2. If the anti-aliasing filter design is 100Ohm or above, the receiving link needs to add RL//CR and select the RLLR network (when selecting RLLR, RL//CR needs to be replaced with RCR); the feedback link needs to add RLLR.
3. First, you need to select C in the RL//CR or RCR network based on the performance test results. Taking H40 as an example, 10pF is used for C in the RL//CR network and 3.3pF is used for C in the RCR network to effectively filter out high-frequency sampling switching noise (in applications where the intermediate frequency IF is less than 350MHz). It is best to use 25Ohm for R in the network, and the principle of L in the network is to make the LC resonant cavity form a resonant frequency near the center of the useful bandwidth.
2. Then, the simulation starts with R1 and R2 being 100 Ohm each. Considering the in-band flatness, the simulation selects the value of RLLR. When the flatness meets the requirements, try to reduce the values ​​of R1 and R2, but increase the equivalent impedance of RLLR appropriately as compensation. Finally, find the minimum values ​​of R1 and R2 under the premise of achieving the combined load target at the ADC end.

ADS58H40 front-end matching network design

ADS58H40 is a four-channel 14-bit, 250MSPS high-performance ADC, which is widely used in the design of wireless base stations, that is, it can be used in the receiving channel and also in the feedback channel. Here, the application of ADS58H40 in a 100Ohm anti-aliasing filter load is used as an example to introduce the front-end matching network design.

4.1 Receive Link Topology

Since the receiving link has high requirements for performance indicators, the RC//LR (RCR) network for absorbing sampling noise is indispensable. In addition, the receiving link bandwidth is narrow, and the RLLR network that adjusts the in-band flatness can be selected. Here, Fs = 245.76MSPS sampling rate, intermediate frequency 3/4 Fs 184.32MHz, bandwidth 80MHz, 100Ohm anti-aliasing filter load application is used as an example. Figure 5 is a simplified front-end matching circuit at the expense of in-band flatness. RL//CR is intended to absorb sampling noise to achieve the best performance optimization. The value of C is preferably 10pF, and the value of L is matched with 10pF to form a resonant cavity within the required bandwidth, which does not attenuate the useful signal and absorbs the high-frequency sampling noise.

Figure 5 Non-input buffer ADC receiver chain design example A – Minimum components sacrifice some in-band flatness

Figure 6 shows a network architecture that compromises performance and flatness. The network architecture is more complex than Figure 5, but the flatness within the 80MHz signal bandwidth is much better than the simplified version design in the above figure. Due to the existence of the front-end RLLR architecture, the RL//CR that absorbs sampling noise is simplified to RCR, and the value of C is preferably 3.3pF.

Figure 6 Non-input buffer ADC receiver chain design example B Optimal in-band flatness

4.2 Feedback Link Topology

The feedback link processes signals with a much higher bandwidth than the receiving link, but the performance requirements are lower than those of the receiving link. In order to meet the requirements of in-band flatness, the flatness adjustment circuit of RLLR is essential. The low-pass or band-pass characteristics of the RC//LR (RCR) sampling noise absorption circuit limit its application in ultra-wideband (BW>100MHz) feedback links. This means that there is also a trade-off between performance and bandwidth in the feedback link. However, considering that the performance degradation of the feedback link is limited at an input amplitude of -10dBFs (the sampling noise increases with the increase of the input amplitude), the performance of the feedback link without the sampling noise absorption circuit still meets the system performance requirements. Here, the application of Fs=245.76MSPS sampling rate, intermediate frequency 3/4 Fs 184.32MHz, bandwidth 200MHz, and 100Ohm anti-aliasing filter load is taken as an example.

FIG7 is a front-end matching circuit of a feedback link that achieves optimal in-band flatness at the expense of some performance, and RLLR is an in-band flatness adjustment circuit.

Figure 7 Non-input buffer ADC feedback link design example

in conclusion

In the application scenarios of high-IF, ultra-wideband, and high-load anti-aliasing filter, the design of the front-end matching circuit of the non-input buffer ADC needs special consideration. According to the different characteristics of the receiving and feedback links, the RLLR flatness adjustment circuit and the RL//CR sampling noise absorption circuit are selectively introduced to achieve a compromise between performance and in-band flatness.