Design of a four-channel high-speed real-time data acquisition system based on TLV1562

1 Introduction

When designing radar clutter cancellers, the traditional method is to use intermediate frequency cancellation, that is, the suppression of clutter is achieved at the intermediate frequency. Early intermediate frequency cancellers often use analog delay lines such as SAW (surface acoustic wave) and CCD (charge coupled device). Due to the outstanding advantages of digital signal processing, especially the development of digital integrated circuits and the increasingly powerful functions of programmable logic devices, digital vector cancellers have become the main working mode at present and in the future. The acquisition and processing of radar signals has become the most critical link. In the design, the author chose the high-speed, low-power reconfigurable TLV1562 with a precision of 10 bits, and realized multi-channel data acquisition and processing at a low cost.

2 System Design and Implementation

2.1 Overall

System Design The system design block diagram is shown in Figure 1. The front-end acquisition system with TLV1562 as the core is part of the entire system. The entire system consists of signal conditioning, signal sampling, high-speed signal processing (digital cancellation) and waveform playback. The signal conditioning circuit compresses and adjusts the signal sent by coherent detection to meet the sampling level of TLV1562; signal sampling is to complete the digitization of analog signals (completed by TLV1562); high-speed digital signal processing is to complete the digital cancellation algorithm in CPLD; the waveform playback part composed of AD7533 is to send the cancellation processed signal to the display screen for display [3.4.5]

Figure 1. Radar canceller system block diagram

2.2 Design of signal conditioning circuit and A/D reference source

Since the analog input signal range of TLV1562 is 0.8~(AVDD-1.9V) for the specified power supply voltage AVDD, the analog signal from the coherent detection must be processed to meet the requirements. In the design, the conditioning circuit shown in Figure 2 is used. R4 is used to adjust the amplitude range of the input signal SIG4, and Vr- is a reference voltage adjusted by TL431 to control the DC voltage of the signal [3].

Figure 2 Signal conditioning circuit

　
TLV1562 has two reference input pins - REFP and REFM. The voltage levels on these two pins are the upper and lower limits of the analog input that produce full-scale and zero-scale readings, respectively. According to the requirements, the reference voltage must meet

the following conditions:

VREFP<=AVDD-1V;

AGND+0.9V
3V>=(VREFP-VREFM)>=0.8V.

Therefore, the reference design shown in Figure 3 is used in the design. By adjusting R31 and R32, VREFP and VREFM meet the above requirements.

Figure 3 Interface timing diagram between EP1K100 and TLV1562

　
2.3 Design of the acquisition system

2.3.1 Interface timing diagram

The interface timing diagram of CPLD and TLV1562 is shown in Figure 4. DISTANCE_PULSE is the distance gate pulse with a period of 512μs (80Km) or 1024μs (160Km). SAMPLE_PULSE is the sampling start pulse. Once its rising edge is detected, the acquisition system starts, START is set to a high level, and the CS of TLV1562 is set to a low level. The timing diagram of WR, RD, and INT is the internal conversion mode timing diagram of TLV1562. When WR appears at a low level twice, the configuration of registers CR0 and CR1 is completed, that is, the initialization of A/D conversion is realized. The A/D conversion is completed, and the output low-level signal INT is valid. The signal RD reads the A/D conversion result and resets the INT signal, completing a conversion cycle and starting to prepare for the next conversion.


2.3.2 CPLD implementation of TLV1562 interface

Since the TLV1562 chip is a configurable A/D converter, its configuration conversion timing diagram is shown in the figure. Therefore, how to use CPLD to implement the configuration and reading and writing of TLV1562 is one of the key technologies. The reading and writing control of TLV1562 is easy to implement, but its configuration is more complicated because it is a four-channel cyclic acquisition. There are two registers in TLV1562 that need to be configured, that is, there are two writes, and the data configured each time is different (see Table 1), so data should be provided accordingly each time it is written. The entire configuration process is implemented in VHDL language using a finite state machine. Five states are defined, namely st0, st1, st2, st3, and ST4. St0 is the idle state, st1, st2, st3, and ST4 are the states of the corresponding acquisition channels, and INDEXREG[1..0] is an identification code used to monitor the number of times the write signal is written. The program is as follows:

Table 1 Control register configuration table

3

Conclusion The design and implementation of a multi-channel high-speed acquisition system based on TLV1562 and EP1K100 are described in detail. The acquisition system is applied to the radar digital canceller, and the results show that both the accuracy and speed can meet the requirements. The multi-channel data acquisition and processing is realized at a lower cost.