Design of a highly efficient and compact flyback converter for telecom power supply

1. Introduction

　　As we all know, telecom power supplies are required to operate over a wide input voltage range (36V to 77V), with the best circuit performance at 48V input. However, this circuit design should be compact, efficient, and have a low profile so that it can fit between tight card slots. This article will discuss a 5W flyback converter switching power supply for telecom applications, which is based on the universal offline power supply controller, the MAX5021 chip (IC1).
　　Today's telecom systems contain many line cards, which are connected in parallel to a high-power backplane, each with its own input filter capacitors and low-voltage power converters. The parallel connection of a large number of input filter capacitors limits the value of each to only a few microfarads, making power supply design quite difficult. So how to solve it?
　　At present, the MAX5021 control chip is a high-frequency, current-mode PWM controller that is very suitable for isolated telecom power supplies with a wide input range. It can be used to design small and efficient power conversion circuits. The features of the MAX5021 chip are: a fixed 262kHz switching frequency that can control the switching loss within an appropriate range while moderately reducing the size of the power components; a large hysteresis undervoltage lockout circuit inside the chip, with extremely low startup current, this low-loss design is very suitable for power supplies with a wide input voltage range and low output power; cycle-by-cycle current limiting (implemented by an internal high-speed comparator) reduces the over-design requirements for MOSFETs and transformers; and also includes features such as maximum duty cycle limiting and high peak output and absorption current driving capabilities. As shown in Figure 1, it is a schematic diagram of a 5W flyback converter switching power supply with an input voltage range of 36V to 72V using a universal offline power supply controller-MAX5201 chip. The design ideas of several major components of the offline switching power supply are discussed below.

2. Power stage design

　　The first step in power supply design is to determine the conversion topology. The conditions for selecting the topology should include the input voltage range, output voltage, peak current in the primary and secondary circuits, efficiency, appearance parameters and cost.
　　For a 5W output power supply with a 1:2 input voltage range, the flyback topology is the best choice. Why? Because this topology requires the least number of components, which is conducive to reducing cost and form factors. The flyback transformer can be designed for continuous or discontinuous operation. In discontinuous mode, the transformer core completely transfers its energy during the off cycle, while the continuous mode starts the next cycle before the energy transfer is completed. In this case, the discontinuous mode is selected for the following reasons: it maximizes the energy storage in the magnetic components (thus reducing the component size); simplifies the compensation (no right half plane zero); and has a higher unity gain bandwidth.
　　Although one disadvantage of the discontinuous mode of operation is the higher peak/average current ratio in the primary and secondary circuits. The higher ratio means higher RMS (equivalent series resistance) current, resulting in higher losses and lower efficiency. Despite this disadvantage, for low power conversion, the advantages of discontinuous mode are clearly greater than the disadvantages. Moreover, the drive capability of the chip is sufficient to drive the power switch tube-MOSFET (Q1) that can carry the peak current. For telecom power applications, the MAX5021 uses standard MOSFETs in this topology and can easily achieve a 15W power output.

3. Design of flyback transformer T1

　　The key to reducing losses and improving efficiency in transformer design is to choose a suitable core. The product of the core and winding area determines the power that the transformer can handle and its temperature rise. When selecting a core, you also need to consider the topology (the ratio of the average current in the winding to the RMS current), output current, efficiency, and shape parameters. The following will explain step by step how to design a discontinuous mode flyback transformer T1/NS_A.
　　* Estimate the minimum area product AP and the core cross-sectional area Ae that meet the requirements, and select a core and bobbin with appropriate shape parameters.
　　* Calculate the secondary winding inductance, which should ensure that the energy stored in the core is fully released within the minimum off time.
　　* Calculate the primary winding inductance based on the energy required to supply the maximum load.
　　* Calculate the primary turns Np.　　
　　* Calculate the secondary turns NS and the bias winding turns Nbias.
　　* Calculate the core AL value.
　　* Calculate the primary RMS current and estimate the secondary RMS current.
　　* Consider proper winding sequence and transformer construction to reduce leakage inductance.

　　3.1 Estimate the minimum area product required to meet the requirements using the following equations:

　　Note that the first equation above is general; the second equation is specific to the case of a power supply using the MAX5021 at a temperature rise of 40°C.
　　Where:
　　
        η = desired converter efficiency;
　　Kp = area allocated to the primary winding (usually 0.5);
　　KT = ratio of primary RMS current to average current (usually 0.55 to 0.65 for discontinuous flyback topologies);
　　KU = window fill factor (0.4 to 0.5);
　　J = current density (9.862x
) at which the window temperature rise is below 40°C); and BMAX = maximum operating flux density (in Teslas, usually 0.12T to 0.15T).
　　Select a core with an area product (AP) equal to or greater than the value calculated above, and note the cross-sectional area of ​​the core. The following table gives the core size, Ap and core cross-sectional area (Ae) corresponding to different output powers:

　　According to the above formula calculation and the output power (5W-8W) selected in the table, it is obtained: Select EPC-I3 type (TDK model - PC44EPCI3-Z) core　　The core
　　Ap and Ae are:


　　3.2 As discussed earlier, the non-continuous operation mode requires the core to be completely discharged during the off cycle. The secondary inductance Ls determines the time required for the core to be completely discharged. After calculation, Ls is:


　　3.3 The current rising in the primary winding during the on cycle builds up a certain amount of energy in the core, which is released in the subsequent off cycle to provide output power. The primary inductance Lp must store enough energy during the on period to support the maximum output power.
　　After calculation, Lp is: 3.4 The next step is to calculate the number of turns _Np


　　of the primary winding . It must be ensured that the maximum flux density of the primary winding does not exceed the upper limit under the action of the maximum Vs area. The maximum peak operating current occurs at the maximum duty cycle. The primary turns _Np is calculated as: Np ₌ 48 　　3.5 Round the primary turns to the nearest integer, and calculate the secondary winding Ns and the bias winding turns NBIAS based on the rounded primary winding turns. The secondary winding Ns and the bias winding turns NBIAS are calculated using the formula _: Ns ₌ 9; Nbias ₌ 20 　　The forward voltage drop of the secondary and bias circuit rectifier diodes is assumed to be 0.2V and 0.7V respectively. Please refer to the data sheet provided by the diode manufacturer to verify these data. Similarly, round the secondary and bias winding turns to the nearest integer.





　　3.6 The AL value of the core is related to the air gap in the magnetic circuit. Most of the energy is stored in the air gap during the conduction of the MOSFET. To reduce electromagnetic radiation, the air gap can be opened on the center leg of the core. The calculated core value AL is:


　　3.7 The transformer manufacturer must also know the RMS current in the primary, secondary and bias windings in order to determine the wire diameter. Considering the skin effect, it is recommended to use a wire diameter of no more than 28AWG. Multiple wires can be wound in parallel to achieve the required wire diameter. Multi-wire windings are very commonly used in high-frequency converters. The maximum RMS current in the primary and secondary windings occurs at 50% duty cycle (minimum input voltage) and maximum output power. The formula can be used to calculate the primary RMS current (IPRMS) and secondary RMS current (ISRMS):

　　The bias current is usually less than 10mA, so the main consideration when selecting the wire diameter is the convenience of winding rather than its current carrying capacity.

　　3.8 In order to reduce the leakage inductance spike when the switch is turned off, reasonable winding technology and sequence are very important. For example, the secondary winding can be sandwiched between the two halves of the primary winding, and the bias winding can be placed close to the secondary winding, so that the bias voltage will follow the output voltage.
It should be noted that:
　　* In the above calculation value of the flyback transformer T1, the calculation formula is omitted except for the one in the title 3.1; the
　　calculation specifications are performed under the conditions of VIN=36V-72V, VOUT=5.1 and IOUT=1.1A.

4. MOSFET (Q1) selection

　　The selection criteria of MOSFET include the maximum drain voltage, peak/RMS primary current and the maximum power dissipation allowed by the package (without exceeding the junction temperature limit). The voltage borne by the MOSFET drain is the sum of the input voltage, the reflection of the secondary voltage through the transformer turns ratio, and the leakage inductance spike. Figure 2 describes the relationship between the drain voltage VDS and the primary current. The maximum rated VDS of the MOSFET must be higher than the worst-case drain voltage (maximum input voltage VIN(MAX) and output load, and VSPIKE=voltage spike).

　　A lower maximum VDS rating means a shorter channel, lower RDS(ON), lower gate charge, and smaller packages. Therefore, it is advisable to reduce the VDS(MAX) requirement by choosing a lower Np/NS ratio and keeping the leakage inductance spikes to a lower level. A resistor/capacitor/diode (RCD) snubber network can be used to suppress the spikes. The
　　primary RMS current can be used to calculate the DC losses of the MOSFET. The switching losses of the MOSFET are related to the operating frequency, the total gate charge, and the cross-conduction losses during the turn-off process. The cross-conduction losses during the turn-on period can be ignored because the primary current starts from zero in discontinuous conduction mode. It is necessary to derating the MOSFET to avoid damage during power-up and fault conditions. The power loss of the MOSFET is estimated using the following formula:



　　Where:
　　　　QG = total gate charge of the MOSFET (coulombs);
　　　　Vcc = bias voltage (volts);
　　　　tOFF = turn-off time (seconds); and
　　　　CDS = drain-source capacitance (farads).

5. RCD (R11 C10 D3) snubber network design

　　In order to reduce the VDS requirement for the MOSFET, it is recommended to use an RCD snubber on the primary side to suppress the spikes excited by the energy in the leakage inductance. The snubber consumes this energy, which would otherwise be consumed by the MOSFET itself. The capacitor in the snubber must have a high enough capacitance to absorb the leakage inductance energy so that the MOSFET drain voltage does not exceed the allowable range. This capacitor can be calculated using the following formula:

　　Where:
　　　　LL = leakage inductance, provided by the transformer manufacturer. (The transformer designed in this article is usually 1uH to 3uH.) VSPIKE = voltage spike, typically 30V to 50V. IPK = peak primary current, which in this case (worst case) is equal to the current limit threshold divided by RSENSE (sensing resistor).
　　Diode D3 must be a fast switching type with a reverse isolation voltage at least equal to the rated VDS (MAX) of the MOSFET. The resistor should be selected so that the RC time constant is 2 to 3 times the switching period. The power dissipated by the resistor is the sum of the leakage inductance energy multiplied by the frequency, plus the power generated by the DC bias across the capacitor. The power loss PR of the resistor can be estimated by the formula (omitted).
C10-- buffer capacitor R11-- buffer resistor.

6. Input filter (C1 C2 R1) design

　　The input filter reduces the AC component of the converter pulse current, so that the converter presents a DC load to the input power supply. The design parameters of this filter are RMS ripple current capacity, input voltage and the level of AC component allowed to be reflected back to the power supply.
　　Since the non-continuous mode flyback converter needs to absorb the triangular peak current through the capacitor ESR in each cycle, large aluminum electrolytic capacitors are required because they have low ESR and high ripple current capacity. However, for a distributed power supply system, the input filter capacitors of the parallel converters are added together, which may produce unacceptable surge current at startup. As an alternative, you can also use ceramic capacitors to obtain low ESR and high ripple current capacity. At the same time, keep the total capacitance low. The
　　input peak-to-peak ripple voltage includes the voltage drop (ΔVc) caused by the capacitor ESR (ΔVESR) and the capacitor charge loss. For low ESR ceramic capacitors, the ratio of contribution from charge loss and ESR ripple can be made 3:1. The following formula can be used to estimate the capacitor capacitance CIN and ESR:

　　Select a capacitor with sufficient RMS (mean effective value) ripple handling capability without excessive internal temperature rise. Use the following formula to estimate the RMS ripple current ICRMS in the input capacitor:


7. LC output filter (L2 C9) design

　　The output capacitor requirement depends on the peak-to-peak ripple level that can be accepted at the load. The output capacitor in the flyback converter must supply the load current during the switch on time. During the off cycle, as the core energy is released, the transformer secondary winding replenishes the lost charge and supplies the load current at the same time. Similarly, the output ripple is the sum of the voltage drop caused by the output capacitor ESR (ΔVESR) and the voltage drop caused by charge loss during the switch on time (ΔVc). The high switching frequency of the MAX5021 reduces the capacitance requirements. It is recommended to use low ESR tantalum capacitors because they have a satisfactory combination of capacitance and ESR. The capacitance and ESR can be calculated using the following formula:

　　Where:
　　　　D _OFF is the discharge duty cycle, which can be calculated using the following formula:

　　In addition, the di/dt of the secondary current will generate additional spike noise when flowing through the ESL of the output capacitor, which is superimposed on the output ripple. A small LC filter can suppress these low-energy spikes, and it also helps to attenuate the switching frequency ripple. In order to minimize the phase lag effect of the filter and ensure that it does not affect the compensation, its corner frequency should be designed to be more than one decade away from the estimated closed-loop bandwidth. Figure 3 shows the peak-to-peak ripple waveform with and without an LC filter. Use a low ESR ceramic capacitor of luF to 10uF and calculate the inductance using the following formula:

　　Where:
　　fc = estimated closed-loop bandwidth.

8. About the power loss of the power supply

　　High-frequency switching converters can be very lossy because switching losses and DC losses simply add. Careful component selection is necessary to keep switching losses to a minimum. The MAX5021 is designed to operate at a high enough frequency to reduce the size of passive components while keeping switching losses as low as possible. The low startup current and low quiescent operating current of the MAX5021 minimize power losses in the control circuit. To further reduce switching losses and achieve higher converter efficiency, select a MOSFET with lower gate charge and gate-to-drain capacitance, and balance the MOSFET's DC and switching power losses. Figure 4 shows the conversion efficiency of the power circuit of Figure 1 as a function of output current. The DC and switching losses in the MOSFET PMOS can be calculated using the following formulas:

　　Where:
　　　　QG = total gate charge of the MOSFET (nanocoulombs);
　　　　Vcc = VCC voltage (pin 4 of MAX5021);
　　　　tF = turn-off time (seconds);
　　　　VD = drain voltage at turn-off (volts);
　　　　fSW = switching frequency (262kHz); and
　　　　IPK = primary peak current (amperes);
　　　　IPRMS = average effective value of current.
　　　　Using Schottky diodes on the secondary side can achieve low VFB and low reverse recovery losses. The DC loss PD in the secondary diode is calculated using the following formula, ignoring the reverse recovery loss caused by the switching process:
　　　　PD = VFB * Io
　　Where:
　　　　VFB = forward voltage drop of the secondary diode at IPK / 2 (volts).
　　In order to reduce the leakage inductance between the primary and secondary of the transformer, the secondary winding can be sandwiched between the two halves of the primary winding. Using multi-strand windings can reduce the losses caused by the skin effect.

9. Stable control and frequency compensation of output voltage

　　The frequency compensation loop is composed of the output VOUT path through the shunt regulator (error amplifier) ​​IC2-TLV431 AC, the optocoupler IC3-MOC207 and the PWM comparator inside the MAX5021. To achieve stable control of the output voltage. The frequency compensation loop is also closed.
　　Through the optimized circuit board design, a closed-loop bandwidth of 8kHz and a phase margin of 44° can be obtained. By switching the load (from 100mA to 1A within 20us), we can check its load transient response. You will get a small offset and fluctuation in the output voltage during the fast establishment process. An over-compensated converter will increase its response time and cause output voltage overshoot during the opening process.

10. Layout and safety guidelines

　　High-frequency switching converters will generate voltage and current waveforms with high slew rates. In order to minimize voltage spikes and electromagnetic radiation, parasitic inductance in the current loop and printed lines should be minimized. Reasonable component placement is the key to shortening high-frequency lines. Follow these steps to achieve good layout:
　　* Minimize the loop formed by the positive terminal of the input capacitor, the transformer primary, the MOSFET switch, the current-sense resistor, and the negative terminal of the input capacitor.
　　* Keep the gate-drive line from the MAX5021 to the switching MOSFET as short as possible.
　　* Place the RCD snubber component as close to the input capacitor and the MOSFET switch as possible
　　. * Place the ceramic capacitors connected to the MAX5021 Vcc, VIN, and CS pins close to the IC.
　　* Minimize the loop formed by the transformer secondary, the secondary diode, and the output capacitor.
　　* For effective heat dissipation on the printed board, place large copper areas on the MOSFET drain, transformer secondary, and secondary diode.
　　The type of circuit (SELV, TNV-1, TNV-2, or TNV-3) and its pollution level (depending on the environment in which the circuit is located) determine the spacing requirements for the primary and secondary circuits.

References

1. MAXIM Product Selector Guide November 2001
2. Computer Products Inc. Power Conversion Engineering Handbook 1997
3. Computer Products Inc. Power Supply Product Handbook 1996-1997
4. Principle and Design of Switching Power Supply Electronic Industry Press 1999