ESD protection design for USB 3.0 applications

 USB is the abbreviation of Universal Serial Bus, which is currently the most widely used transmission interface for connecting personal computers with other external devices. This interface was originally initiated by Intel and Microsoft. Its biggest feature is that it supports hot plugging and plug-and-play. Users can directly install or load hardware drivers without restarting the computer. It is much more convenient to use than PCI and ISA buses.

    The USB 3.0 interface is divided into the host side and the device side. The host side must be supported before the peripheral device side can be used. Chip giants Intel and AMD have begun to launch south bridge chips that support USB 3.0, Microsoft Windows 7 has also begun to provide drivers that support USB 3.0, and more and more computers and peripheral products on the market have recently been advertised as having USB 3.0 functions. It can be seen that USB 3.0 replacing USB 2.0 is an established trend.

The data transfer rate     of USB 3.0 is ten times faster than that of USB 2.0, which just meets the growing demand for high-quality, large-capacity storage. Whether it is the copying or backup of digital photo documents, movie files, email data or other important data, or even the backup of the entire computer system, it can greatly reduce the time and improve work efficiency. In addition to the application on the computer, most mobile phones and cameras also use USB to connect to the computer to transfer data and use USB for charging.

    In order to achieve a transmission speed ten times faster than USB 2.0, more advanced processes must be used to design and manufacture USB 3.0 control chips, which also causes the USB 3.0 control chip's tolerance to electrostatic discharge (ESD) to drop rapidly. In addition, when USB 3.0 is widely used to transmit audio and video data, there will be more stringent requirements for data transmission fault tolerance, and it becomes necessary to use additional protection components to prevent ESD events from interfering with data transmission. In addition to the transmission speed requirements, another most important feature of USB is plug-and-play and unplug-and-shutdown. However, due to the frequent accumulation of static electricity inside the USB transmission line, some ESD phenomena will inevitably occur during hot plugging. Electronic systems often work abnormally and even cause damage to USB connection port components. Transient noise such as ESD comes from this hot plugging action.

Elements of USB 3.0 port protection components

    ESD protection components must meet the following five requirements to be suitable for use in USB 3.0 ports:

First, the parasitic capacitance     of the ESD protection component itself must be less than 0.3pF, so as not to affect the USB3.0 transmission rate of up to 4.8Gbps. Second, the ESD tolerance of the protection component must be high enough, at least able to withstand the attack of 8kV ESD in the contact mode of IEC 61000-4-2. The third and most important requirement is that during the ESD event, the protection component must provide a low enough clamping voltage, which cannot cause transmission data errors or omissions, or even damage the internal circuit of the system product. Fourth, the on-resistance of the protection component after the action must be low enough. In this way, in addition to reducing the clamping voltage, the biggest advantage is that the component can still maintain a low clamping voltage when it is attacked by high-energy ESD, so as to avoid the situation where the protection component is not damaged but the internal circuit of the system cannot work normally or is even damaged. Fifth, a single chip can solve the ESD protection needs of all signal lines/power lines in the USB 3.0 connection port, especially when used in the Micro USB interface, which will greatly reduce the complexity of the design layout.

    The above five basic requirements are indispensable. If any one of them is not met, the USB 3.0 port cannot be fully protected. However, the design of ESD protection components that meet the above five requirements is quite difficult. It cannot be achieved without a design team with rich experience and solid technology.

    Jingyan Technology has advanced ESD protection design technology and has launched the AZ1065 series ESD protection components specifically for the protection needs of USB 3.0. In order to minimize the impact of the parasitic capacitance of the protection component on the high-speed transmission of 4.8Gbps differential signals, the parasitic capacitance of AZ1065 is less than 0.3pF. Under extremely strict capacitance requirements, any pin can still withstand IEC 61000-4-2 contact mode 10kV ESD attack at room temperature.

    Most importantly, compared with the same parasitic capacitance, AZ1065 has the lowest ESD clamping voltage, which can effectively prevent data transmission from being disturbed by ESD events, so that electronic systems with USB 3.0 connection ports can pass the Class-A IEC 61000-4-2 system-level electrostatic discharge protection test. After measuring AZ1065-06F using the transmission line pulse system (TLP), the ESD clamping voltage characteristics shown in Figure 1 can be observed. Under the ESD attack of IEC 61000-4-2 contact mode 6kV (TLP current equivalent to about 17A), the clamping voltage is only 13.4V, which is enough to effectively prevent system products from having data errors, crashes, or even damage during electrostatic testing. Figure 2 shows the results of the USB 3.0 port equipped with the ESD protection component AZ1065-06F successfully passing the 5Gbps eye diagram test.

     As electronic products become increasingly miniaturized, the area of ​​the printed circuit board (PCB) of the product is also getting smaller and smaller. However, the requirements for more functions make the circuits more complicated, which causes considerable troubles to the product design layout.

    The AZ1065 series provides six extremely low capacitance pins, which can simultaneously protect the two differential pairs (TX and RX) of USB 3.0 and the differential pair (D+ and D-) of USB 2.0, with the advantages of reducing PCB area and layout complexity, and can significantly save system costs. More specifically, the AZ1065-06F is the first to adopt staggered pins, so that the feedthrough method can be used to achieve a perfect design during PCB layout. Figure 3 shows the wiring method of the AZ1065-06F.

       This innovative component pin-out method eliminates many of the hassles associated with wire winding, not only greatly helping to simplify PCB layout work during the product design phase, but also making the layout of differential signal lines more symmetrical, thereby reducing the chance of signal transmission errors.

    Jingyan Technology said that using TVS Array to complete ESD protection of multiple signal/power lines is a design trend for system products. In addition to investing a lot of design resources, the company also cooperates with a number of IC design companies, wafer fabs and packaging and testing plants to develop various TVS Arrays that are most suitable for system products, hoping to break the low cost-performance bottleneck of traditional ceramic protection components/Zener diodes and provide system product designers with professional and diversified ESD solutions.