Based on low-cost compact fluorescent lamp ballast design

Integrated compact fluorescent lamp (CFL) ballasts do not usually require power factor correction (PFC) due to their low power levels. However, as the market demand for this energy-saving product grows, power factor correction will likely become a mandatory standard in the near future. Active PFC circuits require additional control integrated circuits, inductors, diodes, and high-voltage MOSFETs. Passive PFC circuits are less expensive but increase the lamp current crest factor, which reduces the lamp life. The design described in this article uses a simple control circuit to improve the passive PFC circuit, which can achieve a higher power factor while reducing the lamp current crest factor to an acceptable level.

　　Figure 1 shows the schematic diagram of the proposed compact fluorescent lamp ballast design. The ballast includes an AC input stage with EMI filter, a passive PFC stage, a ballast control stage using the International Rectifier IR2520D adaptive ballast control IC, a half-bridge inverter and a resonant output stage. Compared with the existing CFL circuit, the improvement of this design is to achieve higher power factor, lower total harmonic distortion (THD) and acceptable lamp current crest factor by using valley-filling passive PFC circuit and lamp current crest factor control circuit.

　　Figure 1: Electronic CFL ballast circuit using IR2520D. Top: DC bus (yellow); center front: Iinput (red); center back: ILamp (green); bottom: VLamp (blue).

　　The valley-fill passive PFC circuit consists of CVF1-2, DVF1-3, RVF, and CX (Figure 1). During each half-wave of the rectified AC input, capacitors CVF1 and CVF2 are charged in series to 1/2 of the AC peak voltage via diode DVF2 and resistor RVF. The role of RVF is to reduce the peak of the current waveform during the charging process of the capacitor. After the bus voltage drops to Vpeak/2 with the sine wave waveform, the capacitors start to provide output current. At this point, the two capacitors are essentially in parallel and continue to provide load current until the rectified AC input exceeds Vpeak/2 again during the next half-wave. The role of capacitor CX is to filter the half-bridge inverter switching spikes that appear on the DC bus. This valley-fill passive PFC circuit achieves good power factor (>0.9) and low THD (<30%), but its main disadvantage is that the 50% DC bus ripple will cause a high lamp current crest factor, which will shorten the lamp life.

　　Waveforms with RFMIN3

　　ILMAP (Upper), DC BUS (Mid), VLMAP (Lower)

　　In addition to the IR2520D, there is a control circuit consisting of RFMIN2-3, RBUS1-2 and QFMIN that modulates the operating frequency to reduce the lamp current crest factor. If the ballast operating frequency is fixed, the 50% DC bus ripple caused by the valley-fill circuit will produce a high lamp current crest factor because the higher the DC bus voltage, the higher the lamp current produced by the resonant output stage. Since the IR2520D uses a VCO with an externally programmable minimum frequency, the half-bridge inverter switching frequency depends on the voltage on the VCO pin and the resistance of the resistor connected to the FMIN pin (see the IR2520D data sheet at http://www.irf.com). When the DC bus reaches a certain voltage, the base voltage of QFMIN connected to the voltage divider (formed by RBUS1 and RBUS2) will exceed the turn-on threshold of QFMIN, causing QFMIN to turn on. At this time, the parallel combination of RFMIN1 and the series connection of RFMIN2 and RFMIN3 forms a resistor between the FMIN pin and GND. Since the lower the resistance on the FMIN pin, the higher the switching frequency, the inverter switching frequency near the DC bus peak will be higher than the inverter switching frequency at its valley. In this way, the crest factor value calculated by ILAMP(pk)/ILAMP(avg) will be reduced. RFMIN3 is an emitter degeneration resistor that can be used to improve linearity. Without RFMIN3, QFMIN will turn on quickly when the voltage on the base of QFMIN reaches the threshold. This will cause the operating frequency to rise sharply, causing distortion of the lamp current waveform.

　　In summary, this design is a low-cost CFL ballast circuit that can achieve high power factor (0.96), low THD (28.5%), and acceptable lamp current crest factor (1.71). In comparison, typical CFL ballasts have lower power factor (0.56), higher THD (128%), and similar crest factor (1.71). Not only is the control method simple and the number of components is low, but this design also meets all the necessary requirements of a ballast.