Wireless System Implementation Using RF Power Amplifier Drivers

At present, 8Vpp and pulse width modulated RF high voltage/high power drivers can be realized based on 1.2V 65nm CMOS technology. In the operating frequency range of 0.9 to 3.6GHz, the chip can provide a maximum output swing of 8.04Vpp to a 50Ω load at an operating voltage of 9V. This enables the CMOS driver to directly connect and drive power transistors such as LDMOS and GaN. The maximum on-resistance of the driver is 4.6Ω. The duty cycle control range measured at 2.4GHz is 30.7% to 71.5%. By using a new thin oxide layer drain extension MOS device, the driver can achieve reliable high voltage operation, and this new device does not require additional cost when implemented in CMOS technology.

Technical Background

Modern wireless handheld communication radios, including radio frequency (RF) power amplifiers (PAs), are implemented in deep submicron CMOS. However, in wireless infrastructure systems, the large output power levels required require RF PAs to be implemented using silicon LDMOS or hybrid technologies such as GaAs and more advanced GaN. For the next generation of reconfigurable infrastructure systems, switch mode PAs (SMPAs) appear to offer the flexibility and high performance required for multi-band, multi-mode transmitters. However, in order to connect the high power transistors used in base station SMPAs to all the digital CMOS blocks of the transmitter, wideband RF CMOS drivers capable of generating high voltage (HV) swings are required. This not only enables better high power transistor performance, but also allows digital signal processing to be used directly to control the required SMPA input pulse waveform, thereby improving overall system performance.

Design Challenges

The input capacitance of LDMOS or GaN SMPA is usually several picofarads and must be driven by a pulse signal with an amplitude higher than 5Vpp. Therefore, SMPA CMOS drivers must provide both high voltage and watt-level RF power. Unfortunately, deep submicron CMOS poses many challenges to the implementation of high-voltage and high-power amplifiers and drivers, especially the extremely low maximum operating voltage (i.e., low breakdown voltage caused by reliability issues) and high-loss passive devices (e.g., for impedance transformation).

Existing solutions

There are not many ways to implement high voltage circuits. Technical solutions that can achieve high voltage tolerant transistors (such as multi-gate oxide) can be used, but the cost is that the production process is expensive and additional masks and processing steps must be added to the baseline CMOS process, so this solution is not ideal. In addition, to reliably increase the high voltage tolerance, a circuit solution using only standard baseline transistors (using thin/thick oxide devices) can be used. In the second approach, device stacking or series cathodes are the most common examples. However, RF complexity and performance have significant limitations, especially when the number of series cathode (or stacked) devices increases to more than 2 or 3. Another way to implement high voltage circuits is to use drain extended field effect transistors (EDMOS) in baseline CMOS technology as described in this article.

New solutions

The drain extended devices are based on smart routing technology, which benefits from very fine dimensions in the ACTIVE (silicon), STI (oxide) and GATE (polysilicon) areas, and can realize high voltage tolerant transistors, both PMOS and NMOS, using baseline deep submicron CMOS technology without additional cost. Although the RF performance of these EDMOS devices is actually lower than that of standard transistors using this process, they can still achieve higher overall performance in the entire high voltage circuit due to the elimination of important loss mechanisms (such as series cathode) associated with other HV equivalent circuits.

Therefore, the high-voltage CMOS driver topology described in this article uses EDMOS devices to avoid device stacking. The RF CMOS driver is fabricated using a 65nm low standby power baseline CMOS process using thin oxide EDMOS devices without the need for additional mask steps or processes. The fT measured on these devices exceeds 30GHz and 50GHz for PMOS and NMOS, respectively, with a breakdown voltage limit of 12V. High-speed CMOS drivers achieve unprecedented 8Vpp output swings up to 3.6GHz, enabling the driving of wide-bandgap based SMPAs like GaN.

Figure 1 is a block diagram of the driver described in this article. The output stage includes an EDMOS-based inverter. EDMOS devices can be directly driven by low-voltage, high-speed standard transistors, which simplifies the integration of the output stage with other digital and analog CMOS circuits on a single chip. Each EDMOS transistor is driven by a tapered buffer (buffers A and B in Figure 1) implemented by three CMOS inverter stages. The two buffers have different DC levels to ensure that each CMOS inverter can operate stably at a voltage of 1.2V (VDD1-VSS1=VDD0-VSS0=1.2V due to technical limitations). In order to use different supply voltages and allow the same AC operation, the two buffers are constructed exactly the same and are built into separate Deep N-Well (DNW) layers. The output swing of the driver is determined by VDD1-VSS0 and can be arbitrarily selected to any value that does not exceed the maximum breakdown voltage of the EDMOS device, while the operation of the internal driver remains unchanged. A DC level shift circuit separates the input signal of each buffer.

Figure 1: Schematic diagram of the RF CMOS driver circuit and the corresponding voltage waveforms.

Another function of the CMOS driver is the pulse width control of the output square wave, which is achieved by pulse width modulation (PWM) through variable gate bias technology. PWM control helps to achieve fine-tuning and tuning functions, thereby improving the performance of advanced SMPA devices. The bias level of the first inverter (M3) of buffers A and B can shift the RF sinusoidal input signal up/down with reference to the switching threshold of the inverter itself. The change in bias voltage will change the output pulse width of inverter M3. The PWM signal will then be transmitted through the other two inverters M2 and M1 and combined at the output stage (EDMOS) of the RF driver.

To ensure layout symmetry for the two RF paths before the output stage, all inverters (from M0 to M3) use a uniform PMOS-to-NMOS transistor size ratio. The layout of each widened transistor in all CMOS levels (the total width of the M0 level can reach 4,032μm) is divided into several unit transistor layout parameterized units (P-cells) and optimized for the highest frequency. Each P-cell contains an asymmetric multi-finger transistor (with minimum gate length), a guard ring, and all interconnections to the top-level internal metal. The layout of each transistor is fully scalable.

Additionally, the driver includes large on-chip AC coupling and AC decoupling parallel-plate interdigital metal-edge capacitors. Capacitor Cin, along with two DC input bias lines (BIASa,b), provide DC level shifting. The output can be either DC-coupled or AC-coupled using on-chip capacitors Cout. AC coupling can drive power transistors (such as GaN) that require a negative gate bias. Four thick power lines (VSS0,1 and VDD0,1) are routed inside the chip on top of two thicker metals. Capacitors C0, C1, C2, and C3 are used to decouple the internal power lines. Dedicated ESD protection circuitry is also added to protect the CMOS chip.

The total chip area of ​​the CMOS driver is 1.99mm2, while the active area (EDMOS and buffer) is only 0.16mm2. The prototype die was mounted on a PCB for easy testing and measured under a 50Ω load environment. The time domain signal can be captured using a high-speed digital sampling oscilloscope. Figure 2 shows the time domain waveform of the driver's DC-coupled output at supply voltages of 3V, 5V, 7V, and 9V, and an input sine wave of 2.1GHz. The maximum swing measured under a 50Ω load and 9V supply is 8.04Vpp. The driver's on-resistance was measured as low as 4.6Ω. Figure 3 shows the measured pulse width (in terms of duty cycle) control range as a function of the DC bias level (i.e., BIASa,b-VSS0,1). The figure also shows two time domain waveforms under different duty cycle conditions. A duty cycle control range of 30.7% to 71.5% was observed at 2.4GHz frequency and 5V supply. At frequencies up to 3.6GHz, the RF driver maintained its pulse waveform at 8Vpp. Another measurement at 2.4GHz showed no performance degradation after 24 hours of continuous operation at 5V and 9V supplies.

Figure 2: Time domain waveforms monitored at various voltages at 2.1GHz (VDD1- VSS0 = 3V, 5V, 7V, 9V).

Figure 3: Measured duty cycle at 2.4 GHz.

Compared to previous state-of-the-art CMOS devices, the driver achieves larger output voltage swing and higher operating frequency. In addition, the CMOS driver has similar performance to SiGe-BiCMOS equivalent circuits. Compared to all previous HV drivers, the chip presented in this article has additional pulses with RF control function to improve the performance of SMPA systems.

Conclusion

This article describes the first wideband PWM controlled RF SMPA driver that achieves 8.04Vpp and 3.6GHz operation in 1.2V baseline 65nm CMOS technology. This CMOS driver, which interfaces digital CMOS circuits with high power transistors, can serve as a major building block for the next generation of reconfigurable multi-band multi-mode transmitters for wireless infrastructure systems.