High frequency clock generator based on DDS+PLL technology

1 Introduction

High-performance frequency synthesis is widely used in modern communication, radar, electronic measurement and other technical fields. There are three main frequency synthesis methods:

(1) Direct synthesis method, which uses mixers, frequency multipliers, frequency dividers and bandpass filters to complete frequency arithmetic operations.

(2) Frequency synthesis using phase-locked loop (PLL), although it has the advantages of high operating frequency, wide bandwidth and good spectrum quality, the frequency resolution and conversion rate are not high enough.

(3) The latest frequency synthesis method is direct digital frequency synthesis (DDS). Compared with previous frequency synthesis technologies, DDS has the outstanding advantages of short frequency conversion time, high frequency resolution, continuous output phase, high-precision and high-stability programming, and full digitalization and easy integration.

However, two obvious shortcomings of DDS limit its further application: First, due to the limitation of the highest clock frequency available for the device, the synthesis frequency cannot be too high. The upper limit of the frequency of the output signal is basically in the HF or VHF band, which is lower than the signal frequency obtained by PLL synthesis technology and direct analog synthesis technology; second, the output frequency spurious components are large, and the spectrum purity is not as good as PLL. In terms of basic principles, PLL is an analog closed-loop system, while DDS is a fully digital open-loop system. The two are two different frequency synthesis technologies. Combining the two to form a DDS+PLL combination system to complement each other can achieve application effects that are difficult to achieve with a single technology.

 2 DDS excitation PLL system

2.1 Performance analysis

The commonly used DDS+PLL combination has two methods: DDS excitation PLL and DDS interpolation PLL. No matter which combination is used, high resolution, fast conversion, and wide frequency range output frequency can be obtained. However, in terms of frequency spurious performance, frequency settling time, and circuit complexity, the two combinations have different characteristics. In the combination scheme of PLL interpolation DDS, although the DDS output does not pass through PLL frequency multiplication, it has lower phase noise and better spurious performance, but this scheme needs to filter out the redundant components generated by the mixer, which affects the loop parameters, resulting in complex circuit design and long hardware debugging cycle.

The 600 MHz clock generator in operation uses a frequency synthesis system that uses a low-frequency DDS to excite the PLL. This scheme improves the conversion speed of the PLL by using a high phase detection frequency, and uses the high resolution of the DDS to ensure a higher frequency resolution of the multiplied PLL output. At the same time, the bandpass filtering of the PLL loop can suppress the out-of-band spurious of the DDS. The advantages of this scheme are simple circuit structure, low cost, easy control and easy integration. In order to ensure the spectral purity of the combined system, a bandpass filter is added to the output of the DDS to suppress and eliminate the broadband spurious from the DDS reference frequency. The system schematic diagram is shown in Figure 1.

Through principle analysis, it can be seen that the phase noise of the DDS+PLL system is mainly determined by the phase noise performance of the PLL, while its spurious performance depends on the DDS.

2.2 Phase Noise Measurement

The phase noise of PLL is mainly composed of three parts: the inherent phase noise of VCO; the phase noise of phase detector, loop filter, divider and the phase noise of reference frequency. Among them, the loop frequency division ratio N (N is taken as 20 in this system) has the greatest impact on the output phase noise within the loop bandwidth, that is, within the loop passband, the output phase noise will deteriorate by 20logNdB.

When the characteristics of VCO are idealized, the noise of the integrated phase-locked loop is mainly considered, and the phase noise of the entire loop can be approximated as follows:

Where: fDDS is the frequency value of the input PLL phase detector; NPLL is the phase noise base of PLL, and the NPLL value of PLL frequency synthesis chip ADF4106 is -174 dBc.

The output frequency fout of the clock generator can be changed as needed. When fout is 600 MHz and the reference crystal is 30 MHz, the phase noise of the loop is:

2.3 Spurious characteristics of DDS and suppression methods

2.3.1 Phase truncation spurious caused by phase truncation

The process of causing this spurious is a periodic phase modulation process, so this spurious is phase modulation spurious. For phase modulation spurious, the number of phase truncation bits can be increased to increase its SFDR. Each additional bit can increase the SFDR by about 6 dB.

2.3.2 Spurious due to amplitude quantization error

The waveform sample value sent to the DAC by the DDS is represented by a finite binary number, so the amplitude value is approximately stored, thereby introducing an amplitude quantization error and forming spurious at the output end. This spurious is amplitude modulation spurious.

2.3.3 Spurious due to DAC nonlinearity

The nonlinearity of DAC includes integral and differential nonlinearity and non-ideal dynamic characteristics of DAC. Due to the influence of DAC nonlinearity, harmonic components of the output frequency and mirror components of these harmonics will be generated in the output signal of the DDS, and its spurious level is determined by the performance of the DAC. As the DDS clock frequency increases, it has become the main source of DDS output spurious.

2.3.4 Suppression Methods

The effective method to suppress DDS spurious is to select high-performance, high-clock frequency DDS devices. The high performance here means that the DDS device has taken certain technical measures to suppress the output of its inherent spurious. Through experiments and theoretical analysis, it is known that when the output frequency remains unchanged, as the clock frequency increases, the distance between the spurious and the main frequency will also increase linearly, which provides operability for spurious suppression. According to the principle of DDS, discrete spurious signals are the main reason affecting the spectral purity. All spurious signals are related to the output frequency, and the position of the spurious can also be predicted. Under the same clock signal, different output frequencies produce different frequency spurious positions. In the design of the DDS+PLL combination system, the appropriate clock frequency and output signal frequency should be flexibly selected according to the principle of DDS, so that the spurious situation near the DDS output signal is in a relatively ideal state, thereby improving the spectral purity of the system.

3 System composition and implementation

3.1 DDS uses the AD9854 from Analog Devices.

The AD9854 is a highly integrated device that integrates a 48-bit frequency accumulator, a 48-bit phase accumulator, a sine function waveform table, a 12-bit orthogonal digital-to-analog converter, and modulation and control circuits. It integrates phase modulation, frequency modulation, amplitude modulation, and I/Q orthogonal modulation. The AD9854 surpasses AD's previous DDS products in all aspects and is a DDS chip with great application prospects. Its main features are:

(1) The internal D/A converter and comparator realize orthogonal I and Q outputs.

(2) It has a 48-bit frequency resolution with a step of 1 MHz, and the phase cutoff of 17 bits ensures that the SFDR index can reach 102 dB.

(3) The excellent circuit technology enables the frequency of the synchronous orthogonal signal output to reach up to 150 MHz, and an average of 100 MHz of new frequencies can be generated per second.

(4) The sine signal output can be converted into a square wave by the internal comparator for clock generation.

(5) Provides digitally controlled 14b phase modulation and single-ended PSK data input, 12b I and Q DAC.

(6) In high-speed clock generator applications, if the 12b "control" DAC is combined with the internal comparator, pulse width modulation PWM and static cycle control can be achieved.

(7) Two 12b digital multipliers can achieve digital amplitude modulation, waveform shaping and accurate amplitude control of orthogonal output.

(8) The clock input frequency multiplier with a selectable integer multiple of 4 to 20 can convert the low-speed clock input from the outside into an internal high-speed clock of up to 300 MHz.

3.2 PLL frequency synthesizer

The ADF4106 of Analog Devices is selected. The ADF4106 has a high operating frequency, which can reach up to 6.0 GHz. The chip integrates various important components of the phase-locked frequency synthesizer, mainly composed of low-noise digital phase detector, precise charge pump, programmable reference divider, programmable A, B counter and dual-mode pre-divider (P/P+1). The digital phase detector is used to compare the output phases of the R counter and the N counter, and then output an error voltage proportional to the phase error between the two. There is also a programmable delay unit inside the phase detector to control the width of the flip pulse. This flip pulse ensures that the transfer function of the phase detector has no dead zone, thereby reducing phase noise and reference spurious.

 The high integration performance of the ADF4106 chip allows it to form a complete low-noise, low-power, high-stability and high-reliability frequency synthesizer with only a small amount of peripheral circuits.

3.3 Selection of other devices

The selection of VCO needs to consider several aspects: certain voltage control sensitivity; good linearity of control characteristics; large frequency coverage; low open-loop phase noise; high frequency stability, etc. The size of the loop output phase noise mainly depends on the intensity of the VCO's open-loop phase noise, so the VCO's phase noise performance must be considered. Based on the above reasons, Mini Circuits' broadband low-phase noise device ROS1200 W is selected.

In wireless communication circuits, the spurious generated by the phase detector comparison frequency is usually an integer multiple of the high-frequency channel spacing, and these spurious can cause adjacent channel interference. The loop filter LF uses a third-order passive filter to better suppress spurious.

3.4 Experimental results analysis

The experiment found that the key technical problem of DDS+PLL technology is that the DDS output has many spurious signals, especially the spurious near the output signal cannot be filtered out by the filter, which will affect the system's spectrum purity to a certain extent. The frequency coverage of VCO is an important factor affecting the phase noise of frequency synthesizer. If the frequency coverage of VCO is relatively wide, the frequency synthesizer unit circuit can be reduced, but usually narrowband VCO has better phase noise characteristics than wideband. These requirements are contradictory, so they should be considered comprehensively according to the specific situation. In addition, the influence of different structures of loop filter on loop performance must be considered. The low end of VCO tuning voltage should be used as much as possible to control the generation of output frequency to avoid the reduction of loop noise performance caused by filtering.

In the DDS+PLL frequency synthesis system, there are both digital circuits and analog circuits, and the analog circuits contain intermediate frequency circuits and high frequency lines. The designed digital circuits must meet the design requirements of high-speed digital logic circuits, and the analog circuits must meet the different special requirements of medium and low frequency circuits and high frequency circuits respectively. In view of the overall requirements of the system for the frequency, noise, frequency resolution and other performance of the frequency synthesizer, in the design of circuit practice, effective decoupling and filtering of power supply and digital circuits, large-area grounding, separation of digital ground and analog ground, etc. can appropriately reduce spurious. 

4 Conclusion

This paper proposes a new frequency generator design. DDS+PLL frequency synthesis system has been widely used in recent years because of its unparalleled advantages over other frequency synthesis methods. The clock signal source designed based on the high-precision frequency signal generator of DDS chip AD9854 has been used in scientific research projects. It can be seen that when it is required to obtain high frequency resolution, fast conversion speed and low noise high frequency or even microwave signal, DDS+PLL technology shows strong vitality.

References

1］Kroupa V F. Phase and amplitude disturbances in direct digital frequency synthesizer［J］.IEEE International Frequency Control Symposium，1997： 975979

2］Zhang Juesheng，Zheng Jiyu，Wan Xinping  Phase-locked technology［M］.Xi'an：Xi'an University of Electronic Science and Technology Press，1994

3］Bai Juxian  Low noise frequency synthesis［M］.Xi'an：Xi'an Jiaotong University Press，1995