Design of a single-ended 10-bit SAR ADC IP core

With the rapid development of integrated circuits and digital signal processing technology, we can achieve various signal processing functions in the digital domain with higher precision, faster speed and lower price than in the analog domain. Therefore, analog-to-digital converters have become very important as interfaces between analog systems and digital systems. Among various types of analog-to-digital converters, successive approximation analog-to-digital converters (SAR ADCs) have been widely used because of their low power consumption, medium precision and medium-to-high resolution. SARADC can be divided into single-ended input and dual-ended (fully differential) input based on input. Although a dual-ended SAR ADC circuit architecture can obtain better common-mode rejection ratio and less distortion, and has been widely used, there is still a certain demand for single-ended ADCs in real life, such as the detection of absolute code channel signals in grating rulers. This paper improves the D/A converter based on a common single-ended SAR ADC circuit architecture, reduces the energy consumed by capacitors and switches during D/A conversion without increasing the capacitor area, and reduces the settling time of capacitor array conversion.

1 ADC overall circuit design
The overall architecture of the single-ended SAR ADC designed in this paper is shown in Figure 1, which mainly includes the following four parts: sample and hold circuit (Sample and Hold), comparator (Comp), 10-bit successive approximation register and control circuit (SARLOGIC), and D/A conversion circuit (DAC).

The input voltage Vin is obtained by the sampling and holding circuit to obtain the sampling voltage Vsh. Vsh is compared with the output Vdac of the DAC through the comparator, and the comparison result is passed to the successive approximation register. The successive approximation register outputs the comparison result on the one hand, and controls the conversion switch of the DAC on the other hand to convert the next bit.
1.1 SAR ADC workflow
The workflow of the SAR ADC is shown in Figure 2. It can be mainly divided into the sampling, zeroing stage and the comparison stage.
Step 1: Sampling and zeroing stage. The switch S in the sampling and holding circuit is closed, Vin=Vsh, which belongs to the following stage; the lower boards of the capacitors C1p~C10p and C1n~C10n in the DAC are all connected to GND, the switch EN is closed, Vdac is connected to GND, and the DAC is in the zeroing stage.
Step 2: Comparison stage. The switch Sa in the sample-and-hold circuit is disconnected, and Vsh is the voltage obtained by sampling; the lower plates of the capacitors C1p~C10p in the DAC are connected to Vref, the other switches are not moved, and the switch EN is disconnected. At this time, the output result of the DAC is:

Vsh is compared with Vdac. If Vsh is greater than Vdac, the comparator output is 1, that is, D1=1, and the successive approximation register deflects the lower plate of the capacitor C10n (MSB capacitor) to Vref according to the comparison result; otherwise D1=0, and the lower plate of C10p is deflected to GND. The other capacitors remain unchanged.
Step j: According to the comparison result of the previous step, the output of the DAC is as follows:

Vsh is compared with Vdac. If Vsh is greater than Vdac, the comparator output is 1, that is, Dj-1=1, and the successive approximation register deflects the lower plate of the capacitor C(11-j)n to Vref according to the comparison result; otherwise Dj-1=0, and the lower plate of C(11-j)p is deflected to GND. The other capacitors remain unchanged. Until j=11, the comparison ends and the next conversion cycle begins. 1.2 DAC circuit architecture
The DAC architecture used in this article is shown in Figure 1. It mainly adopts a split binary capacitor weighted structure, and the control signals S0 to S11 generated by the successive approximation logic (SAR) are used to control the DAC switch. Among them:

the traditional capacitor array is very inefficient during the conversion process. To illustrate this point, take a traditional 2-bit capacitor array as an example, as shown in Figure 3, where C2=2C1=2C0. In the zeroing stage, all capacitors are connected to GND and no energy is consumed. After zeroing, when the first bit is compared, the MSB capacitor C2 is connected to Vref, while the other capacitors (C0 and C1) are still grounded, so the output of the capacitor array Vdac=1/2Vref, where Vref is the reference voltage, and the energy absorbed by the capacitor from the reference voltage at this time. When comparing the second bit, the DAC performs two conversions: if Vsh>Vdac, an "up" conversion is performed, that is, C1 is connected to Vref (C1 is initially connected to GND), so Vdac=3/4Vref, and energy absorbed from the reference voltage is required; on the contrary, if VshVdac, an "up" conversion is performed, that is, C1n is connected to Vref (C1n is initially connected to GND), and energy needs to be absorbed from the reference voltage; on the contrary, if Vsh

From the above, it can be seen that the traditional capacitor array consumes the least energy during the "up" conversion and the most energy during the "down" conversion, while the split capacitor array consumes relatively less energy. Through simulation, it can be seen that the average energy consumed by the SAR ADC structure used in this article due to capacitor deflection is about 30% less than that of the traditional SAR ADC.
For ADCs for high-speed applications, an important technical indicator is the DAC settling time. During the "down" conversion process, two capacitors need to be switched in the traditional capacitor array, and any mismatch of the switch that controls the capacitor conversion during the conversion process, whether random or determined, can cause the capacitor array to convert in the wrong direction, and even cause the preamplifier to overload. When only one capacitor changes during the comparison process of each bit of the split capacitor array, it has a good resistance to the skew of the switching signal. Figure 5 compares the settling time of the two capacitor arrays through simulation. From the simulation results, it can be seen that when the width of the split capacitor array and the traditional array switching time is the same, the settling time of the split capacitor array is about 8% faster than that of the traditional array, and the larger the capacitance value, the more obvious the reduction in the settling time.

1.3 Comparator circuit architecture
The simplified comparator structure used in this paper is shown in Figure 6. It consists of three-stage pre-amplifier and latch, and the first and second stage pre-amplifier structures are the same. The offset voltage of the comparator is an important parameter that affects the comparison accuracy of the comparator, which in turn affects the accuracy of the entire ADC. The offset voltage is stored on the capacitor after being amplified by the amplifier, so the gain of the amplifier stage cannot be too large. Excessive gain will saturate the output, so that the voltage stored on the capacitor cannot reflect the true value of the offset voltage. Therefore, each pole of the three-stage pre-amplifier has a small gain, which can also obtain a larger bandwidth and improve the overall response speed of the comparator. However, if the gain of the comparator is too low, it will affect its accuracy. The use of latches is to increase the gain of the comparator and reduce its power consumption, thereby improving the effective accuracy of the comparator.
2 Layout design and system simulation
This design is based on the Cadence Virtuoso layout editing tool to layout and draw the SAR ADC. The capacitor array uses MIM (metal-insulator-metal) capacitors to improve process compatibility and reduce costs. In terms of layout, the capacitor array is laid out in a symmetrical layout, which effectively reduces the capacitor matching error. Since the successive approximation register and control circuit in this paper are digital circuits generated by the Encounter tool using Verilog coding, this paper separates the digital circuit and the analog circuit and isolates them with an electrical ground ring to prevent mutual interference. The circuit layout is shown in Figure 7, and the chip layout area is about 800μmx340μm. Finally, the netlist with parasitic parameters was generated from the layout using Assura software, and post-simulation was performed to verify the impact of capacitor mismatch and parasitic parameters on the accuracy and speed of the circuit. When the sampling speed is 1-MS/s and the signal frequency is 50 kHz, the results of the three process corners of the post-simulation are shown in Table 1. As can be seen from Table 1, the effective number of bits of the ADC is about 9.3 bits, which basically meets the expected goal and can work normally.

3 Conclusions
This paper designs a single-ended 10-bit SAR ADC IP core, analyzes the main framework of the whole system, the digital-to-analog conversion circuit (DAC) and the comparator. The system is simulated using the XFAB 0.35μm CMOS process and Cadence Spectre software. The simulation results show that when the power supply voltage is 3.3 V, the input voltage range is 0-1.5 V, the sampling rate is 1 MHz, and the input signal frequency is 50 kHz, the effective number of bits ENOB is measured to be 9.37 bit, the SNR is 58.69 dB, the SFDR is 72.86 dB, the THD is 67.51 dB, the SNDR is 58.16 dB, and the power consumption is only
4 mW. It meets the design requirements and can be applied to single-ended input signal circuits.