Downslope compensation for step-down converters above 50% duty cycle

The topology chosen for this article is a relatively unfamiliar one: the three-switch forward converter. See Figure 1 for a basic schematic of the power section. Although this topology is patented by TI, it can be used whenever a TI control IC is used in the circuit.

Figure 1 Three-switch forward topology

This topology has many advantages, especially when the input voltage range is 36 to 72 V of the mobile phone battery. The maximum duty cycle of the topology is 67%, which limits the design to a maximum duty cycle of 67% at the minimum input voltage. At the same time, the voltage of the main switch when turned off is limited to the supply rail input voltage. This means that low-voltage FETs can be used with their corresponding low R _{DS ( on )} resistance. This topology also provides a way to recover the magnetic energy in the power transformer and the primary-side leakage inductance, eliminating the need for a high-loss snubber.

Figure 2 Maximum load output inductor ripple at V _IN(min) and V _IN(max)

This converter design is identical to the buck topology in many other respects, but the duty cycle must be limited to 67% to avoid transformer saturation. This limitation can be achieved by choosing a control IC with a programmed maximum duty cycle (e.g., UCC2807-1 , etc.) (see Reference 2). Since this controller has the required duty cycle limiting function, it is the first choice for this application. Therefore, this controller is used in this article and its various features are used for analysis.

The following analysis assumes a theoretical 100W, 3.3V output switching power supply. The maximum peak-to-peak ripple current flowing through the output inductor of this power supply is equal to 10% of the maximum output DC load current of 30A, and the input voltage range is between 36V and 78V. In addition, we also assume that a synchronous rectifier with a forward voltage drop Vfd _of 0.5V is used for the output. The first step is to determine the turns ratio of the transformer. At the minimum input voltage, the duty cycle is at the maximum limit (67%). The voltage required at the output of the transformer can be calculated using the following equation.

If the transformer primary voltage is assumed to be 36V, the turns ratio (Np) is 6.147, so a 6-turn primary is used. The primary is split into two sections, each with 3 turns (see Figure 1). The standard approach is to sandwich the secondary between the two split primary windings, with Q3 also placed between them. With an input of 78V, the transformer output voltage is 12.3V, resulting in a minimum duty cycle Dmin of approximately 31% _. Therefore, the maximum "off" time is equal to

Where f _sw is the planned switching frequency of 200kHz. The minimum output inductor (L1 in Figure 1) to achieve 10% of the ideal peak-to-peak ripple current is:

The output inductance in equation 2 is calculated to be 4.33 µH. For design convenience, we use 4.5 µH. Using this value, the output inductor drop current I _ds can be calculated as:

By calculation, the inductor drop current (I _ds ) is 0.844 A/µs.

At the same time, the peak current of the output inductor at the maximum input voltage is:

Since the maximum peak-to-peak ripple current is defined as the 10% output current, this current is balanced to obtain the rated DC output. The resulting peak current is 31.884 A.

At minimum input voltage, it is possible to determine the differential voltage at LOUT. From this, we know that the rate of change of the output inductance is 0.489 A/µs. Knowing the duty cycle and frequency, we can calculate the time for the current to increase in the output inductor, and thus determine the ripple current at these conditions. Finally, we know that the peak current at minimum input voltage is 31.122 A. The waveforms are shown in Figure 2. These values ​​are almost equal, but if you increase the droop current, they change—in a surprising way. The droop current that must be added to the peak current to obtain the maximum input voltage is:

The drop current that must be added to the peak current to obtain the minimum input voltage is:

See Figure 3, where the effective falling current is added to the current shown in Figure 2. As a result, the effective peak current for the minimum input voltage is higher than the effective peak current for the maximum input voltage, even though the actual peak values ​​are opposite. The peak value of the effective maximum current (including the falling current for the minimum input voltage) is 33.9A, which is the value that must be used to set the current sense resistor Rs. This current (including the falling current converted to the primary current) is 5.658A.

The IC chosen as the controller has a typical current auto-cutoff level of 1.0V, but the tolerance is between 0.9 and 1.1V. To ensure that all cells can provide the required power, use the lower limit and set the Rs value so that its voltage is 95% of the minimum value of 0.9V at 5.658A. This allows a transient safety margin of 5% and sets Rs to 0.15Ω. Of course, there will be power losses of about 5W, which are most likely caused by a current transformer. When using a 100:1 transformer, Rs may increase to 15Ω. In the following content, we assume that such a transformer is used.

Figure 3 Secondary current plus effective falling current

In reality, the drop current (I _ds ) does not flow through either the current transformer or the power transformer, but its impact needs to be considered, as it affects the voltage of the resistor R _{s . Therefore, a resistor R dspri} is added between the resistor R _s and the current sense pin of the IC . At the current sense pin of the IC, a current ramp is injected into the circuit. The existence of this current ramp makes the ramp voltage formed in the resistor R _dspri between the IC current sense pin and the resistor R _s equal to the voltage formed in the resistor R _{s when I ds} is converted into the primary current . We assume that an equivalent drop current is flowing through the resistor R _s , thereby taking into account the power transformer and current transformer winding ratios at the same time. In this case, for the sake of simplicity of calculation, we set the resistor Rdspri to 1kΩ, which is much larger than the resistor Rs.

Next, calculate the dv/dt required by Rdspri:

From this result, we can calculate the current ramp required for the 1kΩ resistor:

This current flow at maximum “on” time results in a peak current of 70.7 µA.

When using a programmable, maximum duty cycle PWM controller such as the UCC2807, it is relatively simple to set the maximum duty cycle to 67% by setting the two timing resistors to the same value, as shown in the data sheet. In addition, the specifications of this component specify that the valley and peak voltages of the timing capacitors are equal to 1/3V _CC and 2/3V _CC respectively . This results in a voltage ramp amplitude of 1/3V _CC . Knowing this, we can now design the circuit to generate a ramp current that can be injected into the current sensing circuit to provide a falling current to the current signal.

Figure 4 shows a circuit for generating the desired current. The circuit is based on the UCC2807-1 control IC, with VDD _set to 11V. The valley and peak voltages of the “triangle” ramp are 3.667V minimum and 7.33V maximum, and the minimum to maximum time is equal to the maximum “on” time. In this circuit, R3 is equal to 2 times R4. This makes the voltage at the base of Q6 equal to 1/3VCC _, which is the valley of the “triangle” voltage. As the voltage at the “triangle” pin swings from valley to peak (2/3VCC), the voltage across R2 varies linearly between 0 and 1/3VCC _{. A} value for R2 is chosen to give a current of 70.7 µA and a voltage of 3.667 V (51.8 kΩ), and then a unity current mirror is constructed using Q5/R1 and Q7/R6. This allows the designer to generate a current sense signal, add the desired current to the current sense signal, and have the correct shape and timing of the 1KΩ resistor.

Figure 4 Circuit for generating the desired R _{dspri current}

in conclusion

The three-switch forward converter has many unique features in terms of energy recovery. It can return magnetic energy and primary leakage energy to the source, eliminating the need for a snubber and reducing the electromagnetic interference common in ordinary forward converters. It also has many advantages over the two-switch forward topology with duty cycles greater than 50%. This article shows you an example calculation. This calculation is necessary when determining the value of the current sense resistor and understanding the impact of the droop current required for stable operation of the buck converter above 50% duty cycle. The article also shows a method to increase the droop current of the converter.

References

To learn more about this article, visit www.ti.com/lit/litnumber (replace “litnumber” with your TI document number) and download the Acrobat® Reader® file to access the following related materials.

Document Name TI Document Number

[1] Lloyd H Dixon, “Current Mode Control of Switching Power Supplies”, TI Power Supply Design Seminar (SEM400), 1985, SLUP075

[2] "Programmable Maximum Duty Cycle PWM Controller", "UCC1807-x/2807-x/3807-x Product Manual" SLUS163