LED display data processing technology

There are two ways to organize memory (Figure 2): ① Packed Pixel Method: All bits of each pixel on the screen are stored in a single memory bank; ② Bit Plane Method: Each bit of the pixel is stored in a different memory bank. Since multiple memory banks are used, they can read out more pixel information at the same time. From the analysis of the two storage structures, the use of bit plane structure is conducive to improving the display effect of LED screens.

The structure block diagram of the entire LED display control circuit is shown in Figure 3. Among them, the data reconstruction circuit completes the conversion of RGB data, combines the same-weighted bits of different pixels together, and then stores them in adjacent units, thereby completing the reorganization of the entire data in the form of bits.

The data reconstruction circuit is mainly composed of four parts: 8-bit data parallel transmission circuit; 8-bit parallel-to-serial conversion circuit; 8-bit data latch circuit; 8-bit plus 1 counter. The 8-bit data of R/G/B are input into the parallel latch by the pixel frequency after synchronization processing, and the 8-bit plus 1 counter outputs the carry pulse LD, and the 8-bit data is latched into the 8-bit parallel-to-serial conversion circuit at the same time. The clock control circuit completes the control of the clock of the parallel-to-serial conversion circuit. After the data is reconstructed, a storage body is no longer a pixel value, but the same weight bits of different pixel values. All the same weight bits are stored together to form a bit plane storage structure in units of bits. When reading out, the adjacent weights of each pixel must be taken out according to the opposite rules.

The read and write address generators must meet strict timing. For the same memory chip, it can be divided into N pieces (a pixel value is represented by N bits), each piece represents a bit plane, and when the pixel is converted and written to the same memory, first write 0 bit, then write 1 bit, and finally write N bits. For a display screen with 8Col×Row dot matrix, each bit plane stores 8Col×Row bits. The internal organization of the memory depends on the logical connection relationship of the pixel tube on the driving screen. According to the memory organization, the read address generator drives the row by the column, and then drives the bit by the row; the write address generator adopts the method of driving the column by the bit and the row by the column, so as to ensure the synchronization of reading and writing, and correctly and synchronously display the original image signal.