Power Management for Computer Peripherals

Standardization requirements

When expanding the functionality of a computer by adding peripherals, standard interfaces are needed to enable full functionality from different vendors. Using wireless communications to increase the functionality of a desktop computer or increasing the memory of a laptop by using more memory sticks allows low-priced entry-level computers to be upgraded or added or subtracted according to individual needs. In the early 1990s, the advent of the PC add-in card standard allowed memory sticks from different vendors to be used in laptops. The formation of the PCMCIA (Personal Computer Memory Card International Association) standardized the interface standards, allowing the use of plug-in add-in cards such as flash memory or hard drives to expand laptop memory. Naturally, many other vendors soon realized that their specialized functions could also be added to these devices via PCMCIA cards.

Manufacturers of storage, communications and gaming applications joined PCMCIA to understand or influence the interface standard so that their devices could be used in laptops. As host systems and card applications diversified, designers soon discovered that they needed to carefully consider the card's operating and startup power requirements to prevent power and system failures. For example, disk drive motor startup or power hold-up capacitors required by many applications are a potential problem. They can cause large inrush currents that overload the host power supply, causing the system to crash or exceed the safe operating area (SOA) of the host power MOSFET power switch. Issues that the PCMCIA standards committee needed to address included voltage, current (including inrush current) and sequencing. Although PCMCIA has long been disbanded, its standardized power supply specifications are still used in various other add-in cards, including PC Cards that replaced PCMCIA cards.

System Design Methodology

Similar to PC Cards, PCI Express (PCIe) addresses the power requirements of add-in cards in a PC. And the same power supply considerations apply, and like PC Cards, PCIe cards can also generate secondary voltages that require sequencing and monitoring depending on the application. In addition, peripherals are still required to prevent inrush currents while their input capacitors are cycled as peripherals are added and removed. Power management has evolved from MOSFET switches implemented by discrete logic circuits and ASIC controllers, controlling one or two voltages, to ASSPs such as hot-swap/soft-start controllers, power sequencers and trackers, voltage supervisors, reset generators, and watchdog timers. However, with different applications requiring different combinations and versions of ASSPs, a comprehensive power management design can be expensive and complex. With hundreds of devices available from many different vendors, choosing the right combination can be a daunting task. As a result, designers often simplify their power management designs, ignoring certain possible fault conditions or assuming that a certain sequence will always occur. As an example, a power management design monitors only the input supply voltage, and then enables the next regulator by the voltage of one regulator being good, thereby powering up the other secondary voltages. To be sure, this approach does not require a separate sequencer and multiple high-precision voltage monitors to monitor each voltage, thus reducing cost and complexity. However, although this sequential power-up method reduces cost and complexity, the response time to a power failure may be significantly delayed, which will cause serious data corruption, produce incomplete data packets and destroy the data that has been stored.

Figure 1 - PCIe power requirements

PCIe defines voltages, currents, and card input capacitance for various slots. Figure 1 shows the PCIe specification, which defines the +12 V and 3.3 V supplies and tolerances, capacitive loads, and maximum currents, including inrush currents for different cards. PCIe also supports hot-plug cards, and careful consideration needs to be given to limiting the startup voltage slew rate for hot-plug cards. Input supplies should be monitored with a voltage supervisor to determine the limits of the voltage slew rate. Although PCIe does not specify power-up sequencing, a standalone application using a secondary power supply may require complex sequencing.

Figure 2 - PCIe boot waveform

Figure 2 shows the startup sequence for a PCIe card. A key parameter, indicated by the arrows, is that the 12V and 3V supplies stabilize within a 100ms period after the card is inserted. 100ms later, the card is enabled by the PCIe bus host sending a PERST# high signal. Typically 100ms is too short to complete the power-up of the secondary supplies on the card and the initialization of large FPGAs, ASICs, and other configuration devices. Pulse stretching or PERST# signal delay is often required to meet the needs of each board.

Figure 3 - Power-off waveform

Figure 3 shows the power-off sequence for a PCIe card. PERST# initiates the shutdown, allowing the device to power down in a controlled manner before the supply voltage decays. If the card is suddenly removed from the slot while powered, the device will suddenly power down, which could have catastrophic consequences. Therefore, boards should be carefully designed so that they can handle sudden removals and power down the board in a controlled manner.

There are a number of challenges to address when designing PCIe power management. For example:

The inrush current varies with each design, but the PCIe maximum supply current specification must not be exceeded for any instant. The magnitude and duration of the inrush current depends on the board's input capacitance and various other factors, such as the startup current of the FPGA or ASIC.

The card may require different hot-swap controller circuitry for each application.

.Timing may be extended to more than 100ms PERST# signal, delaying reset timing, power-on, FPGA configuration time and CPU reset.

The design must be fast enough to respond instantly and power down the board in a hot unplug event without destroying the system.

All power supplies should be monitored for undervoltage and overvoltage conditions to ensure operational data integrity.

.Power sequencing should be flexible as it is unique to each application and needs to be changed as design changes require.

.Boards containing complex chips such as CPUs usually require a stable core voltage before I/O voltage initialization.

Limitations of Discrete Design

How are these challenges addressed? The traditional approach to designing PCIe card power management is to use a discrete solution. Figure 4 illustrates such an approach, where the hot-swap controller, sequencer, supervisor, reset generator, and watchdog timer are all implemented separately. However, this approach has serious drawbacks. Discrete implementations require studying data sheets to select from a wide range of devices. Discrete designs are inflexible because any design change or a different application will require a different combination of discrete components. Timing and control circuits rely on R/C networks, and their timing will change as components, age, and supply voltages change. Finally, discrete designs are slow to respond to fault conditions such as accidental unplugging due to interoperability issues between devices from multiple vendors.

Figure 4 - Discrete implementation of power management

Integrated Solutions

Integration of power management into one system can significantly reduce costs by providing all power management functions while avoiding duplicate implementation of the same functions. Functions that share resources can be combined. For example, multiple voltage supervisors, sequencers, hot-swap controllers, reset generator ICs, and trimming and margining functions can be implemented using one IC. A very accurate bandgap reference can be shared by multiple functions, further reducing costs without sacrificing accuracy and reliability. More importantly, integration will eliminate communication time delays in discrete solutions. Fault response can be achieved in tens of microseconds instead of the hundreds of milliseconds typically required for systems monitored by microprocessors. Trimming, margining, and voltage measurements can be easily implemented by adding an ADC and a DAC.

ASICs can combine some of the discrete components needed for power management. However, they usually require some additional integrated circuits, including a microprocessor, to implement the solution, and also include some functions that are not required for the application. In addition, ASIC-based solutions are difficult to simulate, and as a "fixed" approach, it requires that any changes be implemented outside the board.

Another more efficient approach is to use a single integrated power management IC. By integrating all power management functions, several key issues of discrete solutions are resolved. The internal communication and slow response to system error conditions caused by separate devices from different vendors are alleviated: they can be processed in just a few microseconds. The overall cost is also reduced because key functions are shared by several channels.

For example, the Lattice POWR1014A integrates 10 programmable voltage monitors and uses a bandgap reference to achieve 0.3% voltage monitoring accuracy for all channels.

Figure 5 - POWR10414A structure

The internal clock and built-in digital timer solve the inaccuracies caused by devices using external R/C networks. The digital I/O, programmable timer, and CPLD core monitor PERST# and PRSNT# and generate card-specific timing to ensure correct timing and configuration. Additional signals can be generated based on the inputs to notify the system of reset or brown-out conditions. The POWR1014A contains two charge pumps to control N-channel MOSFETs. The hot-swap function can be easily customized for each application by varying the gate voltage and charge rate while monitoring the system's current and voltage to ensure that PCIe constraints are met. The CPLD core can easily modify the design for various applications, board and vendor changes. The inputs and outputs can be easily configured and the CPLD core programmed using Lattice's PAC-Designer design software.

Summarize

PCI Express has standardized the interface and timing between PCs and add-in cards. Various applications require custom designs for each unique current, timing, voltage, and sequencing function. Discrete solutions are expensive and lack precise timing, low accuracy, reliability issues due to more complex component materials, and flexibility issues once the design needs to be changed. Lattice's POWR1014A integrates PCIe power management into a precise, flexible, programmable and low-cost solution.