Implementation of RS-232 Serial Communication Based on CPLD

CPLD (Complex Programable Logic Device) is a complex user-programmable logic device. It uses a continuous connection structure and predictable delay, making circuit simulation more accurate. CPLD is a standard large-scale integrated circuit product that can be used in the design of various digital logic systems. Development tools such as Quartus II and ISE are powerful and have flexible and diverse programming languages, which shorten the design and development cycle.

With the development of embedded systems , the requirements for data transmission and human-computer interaction communication are getting higher and higher. Serial communication is widely used because of its low resource consumption and mature technology. The interactive communication between the host computer and the embedded chip in the system can be achieved through a dedicated integrated chip as a peripheral RS-232 asynchronous serial interface , such as TI, EXAR, EPIC's 550, 452 and other series UAWT integrated circuits, or UART modules can be easily embedded in FPGAs with Nios systems . However, in the design, users will put forward their own requirements, such as data encryption or only using some functions of UART, that is, requiring a more flexible UART. And sometimes CPLD resources are surplus, and cost considerations will also require the design of an analog UART. For the above two situations, a UART can be made on the rich resources of CPLD to realize data exchange between PC and embedded system .

1 Serial communication protocol

1.1 UART Introduction

Universal Asynchronous Receiver Transmitter (UART). Characteristics of asynchronous communication: no strict clock consistency is required between the sender and receiver, easy to implement, and low equipment cost. It has the advantages of standard interface level specifications provided by relevant industrial standards and is widely used in the field of industrial control .

A frame of character information in asynchronous communication consists of four parts: start bit, data bit, parity bit and stop bit.

This design is based on the data frame structure of RS-232. The data frame structure is set as shown in Figure 1: 1 start bit, 8 data bits, 1 stop bit, and no check bit. Each frame actually transmits 1 Byte of data.

1.2 Custom data packet format

Multiple frames described above can form a data packet. Serial communication is defined based on the RS-232 data frame structure, and transmission is performed in data packets. The packet structure is shown in Figure 2.

This article adopts the structure of sum check. A data packet contains 15 bytes. The first byte is the data packet header, i.e. the handshake character. The second byte is the control character, EE represents the write command, and DD represents the read command. The third to the fourteenth byte are available data. The fifteenth byte is the check character, which should theoretically be equal to the last 8 bits of the sum of the data strings in this data packet.

2 Design

2.1 UART design structure

The author's design adopts modular design. The UART of the scheme is mainly composed of logic control module, baud rate generation module, sending module and receiving module. The baud rate generation module can establish an accurate clock to ensure accurate data sampling and smooth working timing. The logic control module, baud rate generation module, sending module and receiving module complete the following tasks: determining the data start bit, data transmission and reception, serial-to-parallel conversion, establishing handshake connection, judging commands, data verification and other functions.

2.2 State Diagram

The use of serial communication involves a variety of working states in the process of data interaction, and the situations are quite diverse. However, this problem can be easily solved by using the finite state machine (FSM) theory in programming for programming design.

A finite state machine is a hardware sequential circuit composed of a register group and combinational logic. The state of a finite state machine (i.e., a finite number of states consisting of the combination of 1 and 0 states of each bit in the register group) can only transition from one state to another under the same clock transition edge.

The finite state encoding of this design uses a one-hot code, that is, each bit of the register group represents a state (such as "0100", "1000" are two states in the four-state machine). The advantage of this state code is that it avoids state confusion. The state machine uses a Mealy type finite state machine. The next state of this state machine depends not only on each input value, but also on the current state, which is in line with the working principle of UART.

The design of the logic control module, data receiving module and sending module all use state machines, of which the logic state machine is the master state machine and the other two are slave state machines. After determining the various working states and workflows, a state diagram can be constructed, which is convenient and intuitive for subsequent design.

Through the state diagram, the program design block diagram can be easily and accurately obtained as shown in Figure 4.

Better experimental data can be obtained.

3. Design of each module

3.1 Baud Rate Generator

The baud rate must be set for serial communication. The baud rate used in this design is 9600 bit/s. The higher the clock frequency that generates the baud rate, the better, so that a higher and more accurate baud rate can be generated. The design uses a 50M main frequency to generate a baud rate of 9600 bit/s. Each bit of data needs 5208.33 clock cycles to transmit. The closest number is 5208, so the baud rate is 9600.61, and the error is about 0.006%. The bit error rate is very low to ensure normal communication.

Another key issue that the baud rate generator needs to solve is to ensure accurate capture of the start bit "0". Instant and accurate capture of the start bit not only determines whether the communication starts smoothly, but also affects the reliability of the subsequent data sampling process. The solution adopts a 16-division baud rate generator, that is, by dividing the 50 M total clock source, a 9 600x16 Hz clock is obtained for data transmission, so that 1 bit of data is sampled every 16 clock signals. After the Rxd data receiving port receives a signal that jumps from an idle high level "1" to a start bit low level "0", it confirms whether it is a start bit for 8 consecutive division cycles. If it is a continuous low level, the start bit is captured, and 1 bit of data is read every 16 clock cycles thereafter. This method not only ensures the accurate capture of the start bit, but also puts the data sampling point in the center of the data to ensure the accuracy of the data.

3.2 Receiver

After the baud rate generator captures the start bit and starts, the receiver will start working. Its main work is to receive each bit of data, shift the serial data into the buffer register, and store the data into the latch to complete the serial-to-parallel conversion after receiving one byte of data, and send out the char_ok signal to notify the logic control module that one byte of data has been received.

Part of the receiver program is as follows:

3.3 Logical Processing Module

The logic processing module is a decision-making module that simulates UART. It mainly completes the handshake between PC and CPLD, data processing and data verification, status analysis and provides decision-making for the transceiver module.

When the PC wants to send data to the CPLD, it first sends FF to the serial port. FF means that the PC wants to establish a connection with the CPLD. After the CPLD receives this information, the talk signal of the logic module notifies the transmitter module of the handshake status. The transmitter feeds back information to the PC through the serial port. DD means that the CPLD has received the PC's request and agrees to establish a connection. CC means that the handshake is unsuccessful and the PC can send a request again. After the handshake is successful, the PC will send a command character to the CPLD. E1 means write and E2 means read.

Then it enters the data receiving or sending state. After each data packet is received, the logic processing module enters the next state - data verification state. According to the data verification of this design mentioned above, the data verification adopts the sum verification. After the data verification is completed, the logic processing module will give a signal check according to the verification result, notifying the sending module Txd to send feedback information to the PC.

Part of the program of the logic control module is as follows:

The key point in the logic receiving module is the handshake link, which reflects the key to the dialogue between the PC and the CPLD. The subsequent communication between the two is based on this. The timing simulation of the handshake link designed using the above ideas is shown in Figure 5.

Figure 5 Simulation timing

As shown in the figure, when the char receiving register receives a character information through Rxd, it sends out the char_ok signal. After the logic control module knows that it is the handshake information FF, it triggers the handshake success talk signal, and at the next clock rising edge Txd changes from the idle state high level "1" to the start bit "0" to prepare to send feedback information to the PC.

3.4 Transmitter

After receiving the command from the logic processing module, the transmitter sends the corresponding data to the PC. The content sent mainly includes: data correct or handshake success information DD, indicating that the PC continues to operate; data resend or handshake failure CC, indicating that the PC resends the data; and the data that the PC wants to read from the embedded system.

4 Experimental Verification

An embedded system designed for engineering requires the PC to send data to the CPLD. The CPLD uses the MAX7000 series chip EPM7128SLC84-15 from ATREL. The chip has 2,500 usable gate arrays, 128 macro cells, 8 logic array blocks, and 84 user I/O interfaces. The IO operation level of the CPLD is TTL level. The PC serial port level is converted to TTL level through the MAX232 level conversion chip, which establishes the electrical foundation of serial communication. The PC has a data download program written in VC++, with a baud rate of 9600 bit/s. Each data frame contains 1 start bit, 8 data bits, no check bit, and 1 stop bit. The communication data format uses the sum check data format mentioned above and is sent in data packets, as shown in Figure 6.

Figure 6 Data download

From the experimental results, we can see that every time the PC sends a complete 15-Byte data packet, the CPLD replies with a successful handshake and correct data verification, indicating that the design is feasible.

5 Conclusion

This paper starts from the actual engineering design, and does not select a general UART chip. By analyzing the structural characteristics of UART in asynchronous communication, the rich resources of CPLD and some engineering technologies are used to produce a serial communication module with a custom communication data packet format. Through the joint test with the data transmission program on the PC, the transmission of information and human-computer interaction are realized, proving the correctness of the design. Nowadays, embedded technology is widely used and the market demand is very broad. The communication between PC and embedded system realizes human-computer interaction and makes the system function more powerful. The research is of great significance to enhance the operability of embedded systems.