How to handle high di/dt load transients (Part 2)

In How to Handle High Di/dt Load Transients (Part 1), we discussed the capacitive bypassing requirements of some loads when current changes rapidly. We found that it was necessary to place low equivalent series inductance (ESL) capacitors close to the load because less than 0.5 nH can produce an unacceptable voltage surge. In practice, achieving this low inductance requires placing multiple bypass capacitors and multiple interconnect pins in the processor package. In this article, we will discuss the bypass capacitor size required to achieve the actual di/dt requirements of the power supply output.

For discussion purposes, Figure 1 shows a P-SPICE model of the power system. This figure consists of the compensation circuit power supply, modulator (G1), and output capacitors. It also includes interconnect inductance, bypass capacitor load models, DC loads, and step loads.



Figure 1 Simple P-SPICE Models to Aid System Design

First, you need to decide whether to treat the power supply and load as separate "black boxes" or to approach the problem as a complete power system design. If you use a system-level approach, you can use load bypass capacitors to reduce the power supply output capacitance, thereby saving system cost. If you use the "black box" method, you test the source and the load separately. Regardless of which method you use, you need to know how much bypass capacitance the load requires.

First, estimate the interconnect inductance and resistance between the source and the load. This interconnect impedance (LINTERCONNECT) forms a low-pass filter around the bypass capacitor (CBYPASS). We assume that the source output impedance is low. Using the characteristic impedance (ZO) of this low-pass filter, the load step value (ISTEP), and the allowable voltage fluctuation (dV), establish the bypass filter requirement (Equation 1-2):

Equation 1

Equation 2

Solving Equation 2 for Z0 and substituting it into Equation 1 yields Equation 3:

Equation 3

Interestingly, the required capacitance is related to the square of the load current divided by the square of the allowable fluctuation, so calculate these two values ​​carefully.

Interconnect inductance can range from tens of nH for parallel sources to hundreds of nHs for sources placed remotely. A good rule of thumb is to add about 15 nH of interconnect inductance for every inch. With a load step of 10 amps and an allowable perturbation of 30mV, the bypass requirements range from 500 uF for 5 nH to 50 mF for 500 nH.

In addition, this filter reduces the rate of rise of the load current of the power supply. If the lossless filter is excited by a current square wave, the inductor current is sinusoidal. The rate of rise can be calculated by differentiating the current waveform in equations 4-7.

Equation 4

Equation 5

Equation 6

Equation 7

With an interconnect inductance of 5 nH and a bypass capacitor of 500 uF, a 10 amp step change results in a 0.2 A/uS supply current rise rate. Larger inductance produces lower di/dt. These values ​​are much smaller than what the system designer specified.

When using a system-level approach, the goal is to minimize the total capacitance while maximizing the loop bandwidth. Now, think about how to use the "black box" approach. You must stabilize the power supply without bypass capacitors and with the maximum expected bypass capacitance. As mentioned earlier, interconnect capacitance drives up the bypass capacitance requirements of the load. This in turn affects the capacitance of the power supply when using the “black box” approach. The range of connected capacitance determines the crossover frequency range of the power supply. The two are proportional in both voltage and current modes. You can maximize the crossover frequency with no load capacitance, but as soon as a load is connected, the crossover frequency drops dramatically.

Table 1 compares the required capacitance for three interconnect inductances of the example system. The comparative data was obtained by varying the interconnect inductance, calculating the load bypass capacitance, and designing the output stage and control loop of the power supply accordingly. Case 1 has the load and power supply placed side by side; Case 2 has a moderate interconnect inductance between the power supply and load. Case 3 has a very high inductance with a cable connection. The amount of bypassing required is directly related to the interconnect inductance. In

this case, Case 3 is 100 times the interconnect inductance, and so is the bypass capacitance. This creates ripple in the power supply design because the power supply must be stable with and without bypass capacitors. Obviously, the first approach is better because it uses the fewest capacitors and is the lowest cost. In Case 2, the interconnect inductance is somewhat controlled and the number of capacitors is somewhat increased. In case 3, the large amount of interconnect inductance creates a significant cost issue. Cases 2 and 3 also share a benefit: independent power supply testing.



Table 1 Reducing power system cost with a system-level approach

Figure 2 compares the simulated output voltage change during a load transient for small and large interconnect inductance. The small inductance responds with a fast ramp down, while the large inductance does not, taking longer to stabilize. This is due to the higher characteristic impedance and lower resonant frequency. In addition, if the load current regularly jumps at this resonant frequency, very wide and damaging voltage changes will occur.



Figure 2 Voltage ringing becomes a problem with large interconnect inductance

In summary, high di/dt loads require careful bypass design to maintain the power supply dynamic regulation capability. Low inductance interconnects must be used between the load and the bypass capacitors and between the bypass capacitors and the load. A system-level approach can achieve a lowest-cost solution. Many system engineers overlook this cost-saving solution by reducing the power supply capacitance for the sake of system testing.

Later, we will discuss some empirical conclusions to determine the optimal gate drive timing scheme for synchronous buck structures, so stay tuned.