Research and Design of Thyristor Digital Trigger Based on DSP

1 Introduction

The EAST poloidal power supply is one of the main subsystems of the tokamak. It provides the necessary engineering foundation and control means for the generation, confinement, maintenance, heating of plasma, and the control of plasma current, position, shape, distribution and rupture. It plays a vital role in the performance and safety of the device operation, the success and efficiency of physical experiments. Therefore, the poloidal power supply rectifier control circuit has very high requirements for real-time performance and control accuracy. Among them, the trigger control of the thyristor is the key link of the rectifier circuit. The original analog trigger board of the poloidal power supply is limited by speed and performance, and the control accuracy and real-time performance are not ideal. It is impossible to change the α angle once by 60 degrees. Most digital triggers are composed of zero-crossing detection, counters, and pulse distributors. This paper designs a digital trigger with DSP as the control core, which greatly simplifies the composition of the hardware circuit, improves the control accuracy and real-time performance, and the software is easy to debug and has a flexible adjustment range. 2 System composition and hardware flow chart The main circuit of the polar field converter adopts a three-phase bridge-type in-phase anti-parallel rectifier circuit. The output of the transformer is 2 winding outputs, namely A1, B1, C1, A2, B2, C2. The phase difference between A1 and A2 is 180°, so the phase-shifted pulses of the thyristors corresponding to the same position of each rectifier also have a corresponding phase difference of 180°. For each rectifier, there is an alpha controller, so only one of the rectifiers needs to be analyzed. The line voltage of the 3-way synchronous transformer is processed into a square wave by an optocoupler and a comparator, and then becomes a synchronous pulse signal after passing through a resistor-capacitor filter and a Schmitt trigger. The alpha signal is sent by the control room, with a range of 15° to 150°, 0v represents 150°, and 5v represents 15°, while the voltage range of the DSP AD module is 0 to 3.3, plus an op amp, that is, 0v corresponds to 150°, and 3.3v corresponds to 15°.

Figure 1: Structural Schematic Diagram

3 DSP Control Principle and Software Design 3.1 DSP Control Principle The selected DSP chip is TMS320LF2407, which is a DSP chip with high cost performance developed by TI. Its power supply voltage is 3.3V. There are four timers, of which T1 and T3 can be used for full comparator modulation PWM wave, and EVA and EVB each have three capture units. Six capture units are used to detect six synchronous zero-crossing signals. When the synchronous signal arrives, the corresponding capture generates an interrupt, starts the timer, and the ADC samples the α angle, and then the timer generates a trigger pulse. The Alpha angle range of the polar field conversion circuit is 15o ~ 150o, and the DSP input voltage range is 0v ~ 3.3v, and the corresponding linear relationship is Alpha = -135/3.3*u+150. Since 2407 has only four timers, in the design of this article, the trigger pulses of ab and ba phases are generated based on T1, and the corresponding trigger pulse pin when ab crosses zero is PWM1, and the corresponding trigger pulse pin when ba crosses zero is PWM3; the trigger pulses of ac and ca phases are generated based on T3, and the corresponding trigger pulse pin when ac crosses zero is PWM7, and the corresponding trigger pulse pin when ca crosses zero is PWM9; the trigger pulses of these four phases are generated by the full comparator; the trigger pulse of bc phase is generated based on T2, and the corresponding pin is T2PWM; the trigger pulse of cb phase is generated based on T4, and the corresponding pin is T4PWM; the trigger pulses of these two phases are generated by the comparison output of the timer. The principle is as shown in the figure below: T3 has the same principle as T1, and T4 has the same principle as T2. Since ab and ba, ac and ca differ by 180°, T1 and T3 can fully realize the control of their Alpha angles within the range of 15o ~ 150o.

Figure 2: Schematic diagram of trigger pulse generation

3.2 Software flow

When the capture unit detects the synchronization signal, a capture interrupt is generated, the capture interrupt is entered, the timer is started, and counting begins; the ADC is reset, and the ADC is started to sample the value of Alpha. The sampled value is a level signal (u), and the corresponding digital value (D) is: D = 1023 × u/3.3. The count value corresponding to Alpha is calculated according to the preset timer standard system and the system clock, and the count value is loaded into the full comparison register CMPRx (T1, T3) or the comparison register TxCMPR (T2, T4). According to the required pulse width, a count value is added and loaded into the period register TxPR. Set the period interrupt. When the period interrupt is generated, the timer stops counting, and accordingly, the comparison output pulse is also stopped.

The software flow chart is as follows:

Figure 3: Software Flowchart

4 Experimental Results

The thyristor triggering method of the polar field power converter adopts double narrow pulse triggering, so when the second thyristor is turned on, a trigger pulse must be supplied to the previous tube. At this time, only a slight change in the connection method is required to achieve it. According to the order in which the thyristors are turned on, PWM7 is connected to PWM1, T2PWM is connected to PWM7, PWM3 is connected to T2PWM, PWM9 is connected to PWM3, T4PWM is connected to PWM9, and PWM1 is connected to T4PWM; in this way, the double narrow pulse triggering of the thyristor can be achieved.