Two-dimensional numerical simulation of power MOSFET's SEB resistance

1 Introduction
Power VDMOSFET transistors are widely used in power circuits of space systems due to their fast switching speed, high input resistance, good frequency characteristics, high driving capability, and high transconductance. However, they are easily induced by heavy ions in the space radiation environment, causing severe fluctuations in the power converter or power supply voltage, which can lead to catastrophic accidents in the satellite's electronic system. There are many studies on the SEB effect of power VDMOSFET abroad. However, China started late and there are many problems in theory and experiment.
In this paper, the mechanism of SEB effect of power MOSFET is briefly analyzed, and the effect of buffer layer on improving the SEB resistance of MOSFET is studied by using semiconductor device simulation software Medici for 600 V planar gate VDMOSFET. A solution to improve the SEB resistance of MOSFET by using multi-buffer layer structure is proposed, and finally a set of optimized multi-buffer layer structures are given.

2 SEB mechanism and simulation physical model
2.1 Single particle burnout mechanism
The SEB effect mainly occurs in the blocking state of the device. The principle of SEB from bombardment to MOSFET is shown in Figure 1. The electrons in the electron-hole pairs generated by heavy ion bombardment move toward the drain contact under the action of the electric field, while the holes move along the trace toward the p-body under the action of the drain electric field. After entering the p-body, they move laterally and finally flow out through the p-body contact area. Due to the voltage drop caused by the lateral hole flow, the potential of the p-body part far away from the electrode contact area increases, causing the p-body/n-source junction to be forward biased, triggering the emitter of the parasitic npn transistor to inject electrons into the drift region. Since the MOSFET is in a high-voltage blocking state at this time, the injection of electrons will change the space charge distribution, causing the accumulation of electrons at the n-drift/n+-sub junction, shrinking the space charge region, and increasing the electric field strength at the n-drift/n+-sub junction. As the intensity of heavy ion bombardment increases, the plasma filament flow increases, the forward bias of the emitter junction of the parasitic npn transistor increases, and the electric field strength at the n-drift/n+-sub junction increases. When the electric field increases to a certain level, it will stimulate the avalanche multiplication effect, increase the current in the drift region, and further forward bias the emitter junction of the parasitic transistor. This positive feedback effect is repeated and may eventually cause the device to burn out due to excessive current and high temperature.

From the failure mechanism of SEB, it can be seen that the SEB effect can be suppressed from two aspects: ① Reduce the current gain of the parasitic transistor and weaken the transistor effect, mainly including back gate short circuit, p+ injection, enhance the conductivity of the semiconductor under the source region, adopt the source region trenching process, shorten the source region width, reduce the area of ​​the parasitic transistor, etc.; ② Optimize the electric field distribution and increase the critical current of the avalanche multiplication effect at the n-drift/n+-sub high and low junctions. Since there are relatively few studies in this area, and mainly single buffer layer structures are used, a multi-buffer layer structure is proposed here based on the single buffer layer simulation results, and a set of optimization results of a three-buffer layer structure are given.

[page] The device simulation uses the concentration-temperature dependent carrier mobility model, SRH recombination model, Auger recombination model, collision ionization and bandgap narrowing model, and the thermal effect is not considered yet. In order to be closer to the actual situation, the structure of IR 600VN is adopted, and the contact resistance Rp=2.5kΩ and Rn=250Ω are taken respectively.

3 The role of the buffer layer in improving the ability to resist SEB
3.1 No buffer layer
First, the device simulation of the ordinary MOSFET without buffer layer is carried out. The simulation results are shown in Figure 3. It can be seen from the figure that there are 3 inflection points in the static IV characteristics of the device.

(1) Point A corresponds to normal PN junction breakdown. At this time, the drift region is completely depleted, the carrier concentration in the space charge region is approximately the intrinsic excitation concentration, and the electric field at the p-body/n-drift interface is the largest, reaching the critical breakdown value, as shown in Figure 3b, c;
(2) As the leakage current Id increases, the carrier concentration in the drift region increases, and electrons accumulate near the n-drift/n+-sub high-low junction. The electric field there is enhanced until the concentration of electrons and holes reaches the background doping concentration. At this time, the voltage borne by the drift region reaches the highest point, which is point B. As Id continues to increase, the carrier concentration in the drift region continues to increase, the "depletion layer" shrinks, the electron accumulation layer widens, the electric field in the drift region decreases, the voltage borne by the device decreases, and a "negative resistance region" appears. The current at point B is the negative resistance turning critical current IB. The larger the current, the higher the critical irradiation intensity required to enter the secondary breakdown, and the stronger the device's ability to resist SEB. IB is an important indicator of the device's ability to resist SEB;
(3) When Id increases to a certain extent, the electric field near the n-drift/n+-sub high-low junction reaches the critical breakdown electric field, and secondary breakdown occurs, which is point C. If the voltage Uc at point C is higher than the working voltage of the device when it is reverse blocked, the device will not induce secondary breakdown after being irradiated. Therefore, the level of Uc is also a physical quantity that characterizes the device's ability to resist SEB. The higher Uc, the stronger the device's ability to resist SEB. Improving the device's ability to resist radiation is achieved by increasing IB and Uc.

(1) Compared with the structure without buffer layer, the breakdown characteristic curve of single buffer layer MOSFET has two more inflection points E and F. Point E corresponds to the point where the breakdown electric field of the n drift region/n buffer layer high-low junction reaches the maximum, which is called the secondary breakdown point; after that, the buffer layer depletion layer expands until the excess carrier concentration near the n drift region/n buffer layer interface reaches the buffer layer background doping concentration, which is point F.
(2) As the thickness of the buffer layer increases, the distance between points E and F increases; and vice versa. When the thickness of the buffer layer is reduced to a certain extent, points E and F coincide. The coincidence of points E and F can be used as a reference for thickness optimization.
(3) As the concentration of the buffer layer decreases, point E moves toward point B. When the concentration of the buffer layer is low to a certain extent, point E coincides with point B, and point F apparently replaces point B. At this time, the excess carrier concentration in the drift region reaches the background doping concentration of the buffer layer. Since the concentration of the buffer layer is higher than that of the epitaxial layer, the negative resistance critical current IB increases from 3.47x10-5A/μm to 1.37x10-4A/μm.
(4) As the concentration of the buffer layer increases, point E moves toward the negative voltage direction, and point C moves toward the positive voltage direction. When the concentration of the buffer layer increases to a certain value, the potential of point E is lower than that of point C. The breakdown of point E becomes the limiting factor that limits the device's ability to resist SEB. Therefore, for a single buffer layer structure, there is an optimal buffer layer concentration, which is obtained by the equal voltages at points E and C. If thickness optimization (on-resistance optimization) is considered, a simulated thickness is obtained by the overlap of points C, E, and F.
[page]3.3 Multi-buffer layer technology
The use of a buffer layer structure can improve the electric field distribution and improve the device's ability to resist SEB. However, for a single buffer layer structure, optimizing the buffer layer doping concentration can either improve IB or optimize Uc, but it is impossible to improve both at the same time. It is necessary to adopt a multi-buffer layer structure. Using a low-doping concentration buffer layer to improve IB and using a high-concentration buffer layer to improve Uc is the idea of ​​multi-buffer layer technology.

Referring to the optimization idea of ​​single buffer layer concentration, the three-buffer layer structure was simulated, and the results are shown in Figure 5. When there is no buffer layer, IB=3.47×10-5A/μm, Uc=186 V; when there is a single buffer layer, IB=3.47×10-5 A/μm, Uc=355 V; when there are three buffer layers, IB=1.03×10-3A/μm, Uc=536 V. It can be seen that compared with no buffer layer and single buffer layer, the IB and Uc of the three-buffer layer have been greatly improved.

4 Conclusions
The buffer layer structure can improve the device's ability to resist SEB: the low-doping concentration buffer layer is conducive to improving the negative resistance turning critical current, and the high-concentration buffer layer is more conducive to improving the secondary breakdown voltage. The combination of high and low concentration buffer layer structures can improve the device's negative resistance turning critical current and secondary breakdown voltage. According to this concept, a three-buffer layer structure is given, and the comprehensive ability of the device to resist the SEB effect is improved by optimizing the doping concentration and thickness. The simulation results show that with the three-buffer layer structure, the secondary breakdown voltage is approximately three times that of the structure without a buffer layer, and the negative resistance turning critical current is increased by nearly 30 times.