Design of interleaved low voltage and high current DC-DC converters

This paper further reduces the ripple current by staggering n current-doubler rectifier structures in parallel. The switching signal waveform and simulation model of the circuit are given, and the model is simulated using Pspice simulation software, achieving satisfactory results. Finally, it is verified by experiments. This structure is particularly suitable for power supplies in the fields of communication equipment, computers, aerospace, etc.

1 Introduction

In recent years, as the input voltage requirements of computer microprocessors are getting lower and lower, the research on low-voltage and high-current DC-DC converters has received attention from many researchers, and various topological structures have emerged in an endless stream. Synchronous rectification technology, multi-phase technology, magnetic integration technology, etc. are also applied to this field. The author proposes a staggered parallel low-voltage and high-current DC-DC converter, which adopts a symmetrical half-bridge structure on the primary side and a current-doubler rectifier structure on the secondary side. This structure can greatly reduce the current ripple on the filter capacitor, thereby greatly reducing the size of the filter inductor and the size of the entire DC-DC converter. This converter operates in an environment with an input voltage of 48 V and a switching frequency of 100 kHz.

Structural analysis of low-voltage and high-current DC-DC converter with 2-fold current rectification

The circuit schematic of the low-voltage and high-current DC-DC converter with 2-fold current rectification is shown in Figure 1. The primary side adopts a symmetrical half-bridge structure, and the secondary side adopts a 2-fold current rectification structure. When S1 is turned on, SR1 must be turned off and L1 is charged; when S2 is turned on, SR2 must be turned off and L2 is charged, so that the filter inductor current will be shifted and superimposed on the filter capacitor. Figure 2 shows the switch control strategy.

Figure 1 Circuit diagram of low voltage and high current DC-DC converter with current doubler rectification

Figure 2 Switch control strategy

From the above analysis, it can be seen that the two filter inductor currents on the secondary side of the current doubler rectifier structure are superimposed on the filter capacitor, so that the output current ripple becomes quite small.

The synchronous rectifiers in the structure are all driven by external signals, which makes the control very complicated. However, it is difficult to use a simple self-driving method in this half-bridge-current doubler topology because, in this structure, if a suitable point is directly taken from the circuit as the driving signal of the synchronous rectifier, when the driving signal is zero during the dead time, the synchronous rectifier will be cut off. In order to use the self-driving method in the half-bridge-current doubler topology, an auxiliary winding must be used.

Taking a single half-bridge current doubler topology as an example, see Figure 3, VSEC is the secondary voltage of the transformer, Vgs is the driving voltage of the synchronous rectifier obtained by the auxiliary winding, it can be seen that even within the dead time, the driving voltage of the synchronous rectifier cannot be zero, which ensures the application of the self-driving method in this topology.

Figure 3 Self-driven synchronous rectifier circuit and waveform

In addition, since the MOSFET conduction voltage drop will increase under high current conditions, resulting in large conduction losses, multiple MOSFETs should be connected in parallel to reduce losses.

3 Interleaved parallel low-voltage high-current DC-DC converter

3.1 Circuit schematic diagram
In summary, the current doubler rectifier low-voltage high-current DC-DC converter has good performance. On this basis, the interleaved parallel technology is introduced to form a new structure, called parallel low-voltage high-current DC-DC converter, which can further reduce the output current ripple.

Figure 4 is a circuit schematic diagram of an interleaved parallel low-voltage high-current DC-DC converter (taking the simplest two current doubler rectifiers interleaved parallel as an example).

Figure 4 Circuit diagram of interleaved low-voltage and high-current DC-DC converters

3.2 Switching control strategy of the converter
The switching control strategy of the interleaved low-voltage and high-current DC-DC converter is shown in Figure 5.

Figure 5 Switching control strategy for interleaved low-voltage, high-current DC-DC converters

3.3 Performance of interleaved parallel low-voltage and high-current DC-DC converters
First, the biggest advantage of this topology is that the structure of the primary side of the transformer is simplified, and the control becomes very simple. Secondly, the implementation of this method must use a synchronous rectifier circuit, because the implementation of the interleaved parallel circuit requires that the upper and lower potentials of the secondary side of the transformer are positive in turn, and there is only one positive potential in a period of time, and the rest are zero potential. However, in this topology, since the primary sides of the two transformers are connected in series, and the secondary sides are connected in parallel, if a Schottky diode is used as a rectifier, the input voltage will be divided on the primary sides of the two transformers, and the Schottky diode has no gating function, so the waveform on the secondary side of the transformer will be completely symmetrical, and the currents of the upper and lower rectifier circuits will completely overlap, and the purpose of current interleaved parallel connection cannot be achieved. In this

way, a synchronous rectifier is used to complete this function, and the bidirectional conductive characteristics of MOSFET are used at the same time, because the drain-source current of the synchronous rectifier is distributed on both sides of the horizontal axis of the coordinate. The process of this structure is analyzed in detail as follows:

1) S1 is turned on, S2 is turned off; S3 is turned off, S4, S5, S6 are all turned on. Due to the conduction of S4, S5, S6, the lower end of the secondary winding of the first transformer is at zero potential, the upper and lower ends of the secondary winding of the second transformer are at zero potential, the current on the inductor L1 increases, and the current on L2, L3, L4 decreases.

2) S2 is turned on, S1 is turned off; S4 is turned off, S3, S5, S6 are all turned on. Due to the conduction of S3, S5, S6, the upper end of the secondary winding of the first transformer is at zero potential, the upper and lower ends of the secondary winding of the second transformer are at zero potential, the current on the inductor L2 increases, and the current on L1, L3, L4 decreases.

3) S1 is turned on, S2 is turned off; S5 is turned off, S3, S4, S6 are all turned on. Due to the conduction of S3, S4, and S6, the lower end of the secondary winding of the second transformer is at zero potential, the upper and lower ends of the secondary winding of the first transformer are at zero potential, the current on the inductor L3 increases, and the current on L1, L2, and L4 decreases.


4) S2 is turned on, S1 is turned off; S6 is turned off, and S3, S4, and S5 are all turned on. Due to the conduction of S3, S4, and S5, the upper end of the secondary winding of the second transformer is at zero potential, the upper and lower ends of the secondary winding of the first transformer are at zero potential, the current on the inductor L4 increases, and the current on L1, L2, and L3 decreases.

The above formulas all ignore the voltage drop of the rectifier, and VSEC is the voltage value of the secondary side of the transformer.

According to the above analysis, by applying synchronous rectifiers, this staggered parallel half-bridge-current doubler topology can be realized by connecting the primary side of the transformer in series and the secondary side in parallel. Its advantages are mainly as follows:

1) It effectively simplifies the topology and control strategy.
2) When the frequency remains unchanged, if the peak-to-peak value of the ripple is constant, this structure can effectively reduce the value of the filter inductor, thereby speeding up the dynamic response time of the entire converter. 3)
Compared with the non-interleaved parallel half-bridge-current doubler topology, the conduction loss of the primary and secondary sides of the interleaved parallel half-bridge-current doubler topology is almost the same, but due to the use of interleaved parallel technology, the switching frequency of the secondary side is half of the original, and the corresponding switching loss is also half of the original. Since the switching loss of the converter accounts for a large proportion of the entire loss statistics, the interleaved parallel technology can greatly improve the efficiency of the converter.

4 Simulation Analysis

Pspice software is used to simulate the circuit. The parameters of the circuit are as follows: switching frequency is 100 kHz, duty cycle is 40%, input voltage is 48 V, filter inductance is 2 μH, filter capacitor is 820 μF, output current is 60 A, and output voltage is 1125 V.

Figure 6 shows the current waveform of the filter inductor. It can be seen from Figure 6 that the currents of the four filter inductors are charged in turn. If one filter inductor is charging, the other three inductors must be discharged. During the dead time, the four filter inductors are all discharged.

Figures 7 and 8 show the output current ripple waveforms of the interleaved parallel converter and the single current doubler rectifier converter structure, respectively. It can be seen from Figure 7 that the currents of the four filter inductors are superimposed on the filter capacitor, which can reduce the current ripple a lot.

Figure 6 Filter inductor current waveform

Figure 7 Output current ripple waveform of staggered parallel converter structure

Figure 8 Output current ripple waveform of single current doubler rectifier converter structure

5 Experimental results

Through theoretical research and simulation analysis, it can be seen that the staggered parallel low-voltage high-current DC-DC converter has good performance. When the output is 1125 V/60 A, the output current ripple can be reduced to a very small level. In order to further illustrate the feasibility of this topology, the experimental results are used for verification. The experimental circuit is shown in Figure 4. The experimental parameters are the same as the simulation. Finally, the experimental waveform shown in Figure 9 is obtained. In Figure 9, Vgs is the gate drive voltage waveform of a MOSFET on the primary side, and Vds is the gate-source voltage waveform of the corresponding MOSFET. It can be seen from Figure 9 that the waveform obtained by the experimental results is very consistent with the theoretical analysis results of Figure 5. The proposed method is feasible. Among them, the transformer uses the GU22 core made of R2KB soft ferrite material, and the number of turns of the primary and secondary sides are 8 turns and 1 turn respectively; the inductor uses the ring core T5-10-215 made of wide constant magnetic material IJ 50h, and the number of turns is 8 turns.

Figure 9 Experimental waveform

6 Conclusion

Through simulation and experimental analysis, the following conclusions are drawn: For low-voltage and high-current DC-DC converters, the output current ripple can be further reduced by interleaving in parallel, and the effect is very obvious; or under the same output current ripple, the filter inductance value can be greatly reduced, thereby reducing the size of the entire converter and improving the transient response characteristics of the converter. The case of interleaving in parallel of two current-doubler rectifier structures discussed is also applicable to the case of interleaving in parallel of multiple current-doubler rectifier structures.