Delta-Sigma A/D Converter Principle and PSpice Simulation 2011-11-21

Delta-Sigma A/D converters have the characteristics of high resolution, high integration, low cost and easy use. In recent years, they have been widely used due to the surge in demand for high-resolution A/D and D/A converters in digital products. The concept of Delta-Sigma A/D converters has been around for many years. In the early days, it was not widely used in products due to the limitations of integrated circuit manufacturing technology. As the cost of integrated circuit manufacturing continues to decrease, the application of this technology has gradually increased, and it has now become the mainstream technology for high-precision ADCs. As this technology becomes more popular, more people want to understand its working principle, but domestic textbooks currently do not cover it much, and journal articles mostly focus on mathematical deduction, and there are no detailed simulation examples in the literature.
In addition to manufacturing dedicated ADCs, this technology is also easy to implement with FPGAs. The logic circuit can be fully integrated inside the FPGA, and only a few peripheral components are needed to directly use FPGAs for mixed signal processing. Due to the scalable and reconfigurable characteristics of FPGAs, it is particularly suitable for product development and small-scale production. In addition, it is also easy to use FPGAs to implement multi-channel Sigma-Delta A/D conversions on a single chip.
Delta-Sigma is sometimes called Sigma-Delta, or ∑-△.

1 Delta-Sigma A/D Converter Principle
In a Delta-Sigma A/D converter, an analog input voltage signal is connected to the input of an integrator. A voltage change rate, or ramp, is generated at the output corresponding to the input size. The ramp voltage is then compared to the ground potential (0V) by a comparator. The comparator behaves like a 1-bit A/D converter, generating a 1-bit output ("high" or "low") depending on whether the integrator output is positive or negative. The output of the comparator is latched by a D flip-flop driven by a very high frequency clock and fed back to the other input channel of the integrator, driving the integrator towards 0V. The basic circuit is shown in Figure 1.

In Figure 1, the leftmost op amp is an integrator. The next op amp that the integrator feeds is a comparator, or 1-bit A/D converter. Next is a D flip-flop, which latches the comparator's output at each clock pulse, sending a "high" or "low" signal to the next comparator at the top of the circuit. This last comparator is used to invert the signal polarity, converting the 0 V/5 V logic level output of the flip-flop to a V+/V- voltage signal that is fed back to the integrator.
If the integrator output is positive, the first comparator will output a "high" signal to the D input of the flip-flop. On the next clock pulse, the "high" signal will be output from the Q line to the amplifier input of the last comparator. The top comparator will see an input voltage greater than the threshold voltage of +1/2 V, and it will saturate in the positive direction, sending a full V+ signal to the other input of the integrator. This V+ feedback signal drives the integrator output in the negative direction. If the output voltage is always negative, the feedback loop will send a correction signal (V-) back to the top input of the integrator, driving it in the positive direction. This is the concept of △-∑ behavior: the first comparator senses the difference (△) between the integrator output and the 0 V voltage, and the integrator calculates the sum of the analog input signal and the output of the top comparator (∑).

2 PSpice simulation
Through PSpice simulation experiments, it is easier and clearer to understand the working principle of the △-∑ A/D converter. Below, PSpice is used to simulate the △-∑ A/D converter. This article uses CaptLire CIS Lite Edition 9.2 to draw the circuit diagram and PSpice Lite Version 9.2 for simulation.

2.1 Draw the circuit diagram
First, use OrCAD Capture to draw the △-∑ A/D converter circuit diagram, as shown in Figure 2. The signal source uses a sinusoidal signal with FREQ=100 kHz. The offset VOFF=0, the amplitude is first set to 0 V, and AMPL=0.

For convenience, all operational amplifiers in the figure use the uA741 model, because this model is easy to find. In actual projects, the appropriate operational amplifier is selected according to the needs. The D flip-flop uses 74LS74. There is no component symbol library 74ls.olb or simulation library 74ls.lib for the 74LS series in CaptureCIS Lite Edition 9.2 and PSpice Lite Version 9.2. You can download it from the following website:
http://power.teipat.gr/download/OrCAD/OrCAD%20Libraries/Library%20for%20Capture/PSPICE/
The 74LS series is a low-power Schottky type TTL device with a minimum input high level of 2.0 V and a maximum input low level of 0.8 V; the minimum output high level is 2.7 V and the maximum output low level is 0.5 V. R3 and R4 are used to divide the voltage to convert the output voltage of U2 into a voltage of 0 to 3.75 V to adapt to the TTL input level. The 74LS model only accepts positive voltage as a level signal, so the negative voltage output of comparator U2 can be ignored. R6 and R7 divide 15 V to 2.5 V as a reference voltage, and convert the TTL output level of 74LS74 into a voltage signal of V+/V- through U3. The clock of the D flip-flop is provided by DSTM1. From the product manual of 74LS74, it can be seen that when both LCR and PRE terminals are high, at the rising edge of the clock, the D flip-flop sends the data of input terminal D to output terminal Q and latches it to the rising edge of the next clock. This high level is provided by DSTM2. Figure 3 shows the waveforms of STM1 and STM2 displayed in Stimulus Editor. Double-click the waveform to edit it.

2.2 Case where the input signal voltage amplitude is 0 V
Functionally, the conversion result of the △-∑ A/D converter is a serial bit stream output by the trigger. If the analog input is 0 V, the integrator will not have a slope that tends to be positive or negative, and the integrator only responds to the feedback voltage. In this case, the trigger output will continue to oscillate between "high" and "low", and the feedback system searches back and forth, trying to maintain the integrator output at 0 V. Figure 4 is a schematic diagram of the ∑-△ converter running with a 0 V analog input. The square wave in the figure is the output of the D trigger, and the triangle wave is the output of the integrator.

Figure 5 is a simulation of a sigma-delta converter operating with a 0 V analog input.

In Figure 5, the square wave is the serial bit stream output by the D flip-flop, and the triangle wave with a larger amplitude is the output waveform of the integrator. The simulation configuration file settings are shown in Figure 6.
2.3 The case where the input signal voltage amplitude is not 0 V
If a small negative analog input voltage is applied, the integrator will have a tendency to tilt its output in the negative direction. Feedback can only correct the tilt of the integrator with a fixed voltage (power supply voltage) within a certain period of time, so the bit stream output of the flip-flop will not be exactly the same as before. Figure 7 is a schematic diagram of the ∑-△ converter running with a small negative analog input.
Apply a larger negative analog input signal to the integrator, and its output tilts more steeply in the positive direction. In this way, the feedback system will output more 1s than before to lead the integrator output back to 0 V. Figure 8 is a schematic diagram of the ∑-△ converter running with a larger negative analog input.

Parallel binary outputs can be obtained from this circuit by averaging the serial bit stream. For example, a counting circuit can be used to collect the total number of flip-flop outputs 1 (the total number of outputs 0 due to the positive input voltage) in a given clock pulse, and the value of the counter can be used to represent the analog input voltage. Figure 9 is a simulation of a sigma-delta converter running with a 5 V analog input.

In the figure, the sine wave is the input signal, the square wave is the serial bit stream output by the D flip-flop, and the triangle wave is the output waveform of the integrator. Figure 10 only shows the input signal and the D flip-flop output.

From Figure 10, we can clearly see that the input signal modulates the output pulse width and frequency. The output is a 1, 0 bit stream whose duty cycle changes with the analog input voltage.

3 PSpice simulation of the adjustment of the integrator parameters for input signals with different voltage amplitudes
For input signals with different amplitudes, it is necessary to modulate the parameters of the integrator to improve the accuracy of A/D conversion. Figure 11 is an ideal integrator and its input/output formula, where RC is the integration constant of the integrator.

Corresponding to the circuit in this article, R1, R5 and C1 determine the time constant of the integrator, R1C1 is the integration constant of the input signal, and R5C1 is the integration constant of the feedback signal. Changing the value of resistance or capacitance will change the conversion accuracy. Changing C1 will change the time constant of the input signal and the feedback signal at the same time. When the amplitude range of the input signal changes, it is better to improve the conversion accuracy by changing R1. The influence of the integrator time constant on the conversion accuracy can be seen by scanning the parameters of R1.

Through parameter scanning analysis, it can be seen that the increase in resistance reduces the strength of the input signal, the distance between pulses decreases, and the pulses contain fewer "0" or "1", indicating that the conversion accuracy is reduced. However, R1 cannot be too small. If R1 is too small, some pulses will be lost at the corresponding high input signal amplitude, that is, data will be lost. The selection of the time constant should be repeatedly simulated according to the amplitude range of the input signal waveform in actual needs to obtain the best parameters, and then determined by actual circuit testing.

4 Simulation example of small signal input
When explaining the principle of the ∑-△ converter, the input signal voltage amplitude is 5 V. In many cases in actual applications, the input signal is in the millivolt level. The following simulation is performed on a sinusoidal signal with an amplitude of 0.05 V (50 mV). The parameter simulation method is used to determine R1=1.1kΩ. The simulation results are shown in Figure 12.

5 Conclusion
∑-△A/D converter has very high resolution and low noise. Because it uses oversampling technology, the requirements for the front-end anti-aliasing filter are greatly reduced. Generally, a simple RC low-pass filter is sufficient. The linearity of this type of ADC is also very good. It has become the main way to achieve high-precision A/D conversion, but the price it pays is the reduction of sampling rate. In addition, since the internal filter requires a relatively long settling time for the sudden change of analog signals and the switching of channels, and there is a long delay between the output data and the analog input, this type of A/D converter is suitable for applications where the analog signal is close to DC or changes very slowly, such as temperature measurement, pressure measurement, etc., and has also been used in the audio field in recent years.