Design and Implementation of Radar Multifunctional Interface Module Based on SOPC

In order to meet the requirements of high performance and miniaturization, SoPC technology is used to implement multiple embedded systems on a FPGA to complete avionics interface functions such as 1553B communication and display processing. In particular, the software-configurable color palette and layered overlay display technology are implemented using VHDL language, making the system have the advantages of high integration, flexible configuration, and high reliability. The main functions, working principles, and key technologies of each submodule are introduced in detail. The module has been successfully applied to the actual system.

0 Introduction
The interface module of the airborne fire control radar must undertake all the interface tasks of the data processor, including communication with the avionics system bus outside the radar, communication with other subsystems inside the radar (such as transmitters, etc.), and output radar video signals to the avionics integrated display. Some of these interface functions are relatively complex, such as the display processing interface, which processes the target, antenna, track, map and other data sent by the radar data processor to form a video signal output that meets the standard. Some require high reliability and real-time performance, such as the avionics bus communication interface. For high-performance military designs, it is required to minimize space, power consumption, and weight. With the continuous development of semiconductor technology, field programmable gate array (FPGA) technology is also constantly improving. Compared with 1999, the cost of FPGA has been reduced by 500 times, the logic capacity has been increased by 200 times, the power consumption has been reduced by 50 times, the speed has been increased by 40 times, and it provides powerful functions such as memory, high-speed parallel and serial I/O, embedded processor, DSP, etc., making its application develop in a wider range of fields. As a special embedded microprocessor system, SoPC combines the advantages of SoC and FPGA, and has the functions of software and hardware in-system programmability, tailorability, expandability and upgradeability. It has gradually become an emerging technical direction. Using FPGA based on SoPC to design embedded computer systems can improve system performance while putting peripheral digital circuit modules and memory into the chip design, greatly reducing the number of chips and maximizing the integration of the system. It is the new technology that can best meet the requirements of miniaturization and high performance. This paper uses Xilinx's 32-bit soft-core MicroBlaze based on Virtex-ⅡPro FPGA and 32-bit PowerPC series processor hard-core PowerPC 405.

1 Application system and external interface
The universal multifunctional interface module designed in this paper includes three interface submodules, namely, the 1553B bus interface submodule (MBI) for communicating with the external avionics system, the communication control submodule (M0) between the radar internal subsystems, and the avionics display interface submodule (TVJ). These submodules are independent of each other and have real-time requirements. For the MBI module, the system needs to be able to respond to external data transmission and reception in real time and have high reliability, and the processing speed may not be very high. For the display control module, the system needs to have a high processing speed and ability to complete the layered overlay display of color radar images and the continuous display of map images. In response to these requirements, SoPC technology is fully adopted, and the three embedded computer systems are all designed and implemented inside the FPGA, which meets the design requirements well. Figure 1 is the overall block diagram of the system. The three submodules are connected to three external interfaces respectively, and at the same time, they independently complete data exchange with the main control computer through the common interface with Multibus.

2 System Function and Implementation
2.1 MBI Submodule Circuit Design
Figure 2 is a block diagram of the 1553B bus interface submodule (MBI) system. Microblaze is a 32-bit core microprocessor of the MBI functional block. It is a RISC embedded soft processor optimized for Xilinx FPGA. It has 32 32-bit general registers, hardware multiplier, 32-bit address bus and 32-bit data bus, three-operand 32-bit instruction word, and the on-chip bus follows the OPB (On-chip Peripheral Bus) standard. OPB is a fully synchronous bus. The OPB bus interface provides a separate 32-bit address bus and 32-bit data bus. The OPB bus is used to expand and control the 1553B protocol chip, 32-bit real-time clock, asynchronous serial port (UART), GPIO and dual-port RAM. A memory interface function with Multibus is designed on the other port of the dual-port RAM1, so that the master devices on the Multibus bus and the OPB bus can access RAM1 at the same time without conflict, and a bidirectional interrupt function can be implemented on the Multibus. In addition, the 32-bit radar real-time clock can also be accessed simultaneously through the Multibus I/O interface and the OPB bus interface without conflict.

In order to flexibly set the working mode of the 1553B protocol chip, a 16-bit GPIO on an OPB bus is used to save and modify the settings of the chip's working mode, including 5-bit RT address RTA[4:0], 6-bit working mode setting MSEL[5;0], chip reset MRST and other controls. Except for the 1553B controller and transformer, all the above circuits are designed and implemented in the FPGA using IP core and VHDL. After the MBI software is powered on, the 1553B controller is initialized, and then the radar data processing host sends commands and data through the dual-port RAM1 on the Multibus and the commands sent on the 1553B bus in real time to complete data exchange and communication with other avionics equipment.

2.2 M0 submodule circuit design
Figure 3 is the system block diagram of the internal bus interface submodule (M0). W8051 is an IP soft core compatible with the 8051 single-chip microcomputer. It realizes the radar internal bus M0 master controller function through the 8051 serial port working in mode 2. The W8051 is expanded with 4 KB of program ROM and 256 B of RAM, and the 4 KB of dual-port RAM2 is expanded and connected to the Multibus to realize data exchange with the main control computer. The main control computer interrupts W8051 through an I/O (INT). The entire M0 control system is implemented inside the FPGA. The software implements a custom M0 internal bus communication protocol on this independent computer system to complete the reliable communication between the main control computer and other radar slave devices (such as transmitters, receivers, etc.) on the internal bus.

2.3 TVJ sub-module circuit design
The core of the TVJ functional block is the FPGA-based hard processor core PowerPC 405. PowerPC 405 is a high-performance 32-bit PowerPC series processor core designed specifically for embedded applications. For Virtex-ⅡPro series FPGAs, its implementation model is PowerPC405D5. Its core structure mainly includes a 5-level pipeline unit, a virtual memory management unit, a cache unit with independent instructions and data, a debug port and 3 programmable counters. The on-chip bus complies with the PLB (Processor Local Bus) standard. PLB is a high-performance synchronous bus used to connect processors and high-speed peripherals, providing separate 32-bit address buses and 64-bit data buses. The PLB bus interface is used to expand the video RAM, color lookup table LUT, 32-bit counter, UART and dual-port RAM3. The other end of the dual-port RAM3 implements the memory interface with Multibus and the bidirectional interrupt function. The video RAM is divided into two blocks, A and B, with a total of 4 MB and a display resolution of 575×575×16 b. They can be read/written through the PLB bus and the multiplexer circuit. At the same time, the content of the video RAM is read out by the read control circuit, converted into 24-bit true color digital video through the color lookup table, and then output as an analog video signal through D/A conversion and the drive of the op amp. The content of the color lookup table LUT can be set at any time through the PLB bus to switch between multiple layered superimposed color display modes in real time. The video timing generation circuit generates synchronization/blanking signals that conform to the PAL standard. When there is an external synchronization signal input, the external synchronization detection circuit can automatically identify it and cooperate with the external phase-locked loop (PLL) to generate a video timing signal that is completely consistent with the external synchronization signal, ensuring that the final output analog video is completely synchronized with it. Except for the video RAM, PLL, D/A, and op amp circuits, the entire PowerPC 405 system and the timing, logic circuits, and color lookup tables for display control are all implemented inside the FPGA, as shown in Figure 4.

2.4 Design of TVJ submodule video control circuit
The video control circuit is the key circuit of the TVJ submodule, which includes the PLB bus interface, VRAM switching control circuit, video timing generator, VRAM address generator, color lookup table and control/status register, as shown in Figure 5.

The PLB bus interface mainly completes the seamless interface circuit between the video control circuit and the system PLB bus in accordance with the IBM CoreConnect bus specification. The VRAM switching control circuit completes the system's alternate switching of the read/write control of the two video memories. PLB_EMC is the PLB bus external memory control interface IP that comes with the Xilinx embedded development kit EDK. VRAM_A and VRAM_B are both video memories that store video image data. The switching control circuit always connects one video memory to the PLB_EMC interface at any time, and reads the video image data from the other video memory and outputs it to the D/A after palette conversion to generate the color image signal to be displayed. When modifying the display screen, the CPU first rewrites VRAM_A connected to the PLB_EMC interface through the PLB bus, and uses the data read from VRAM_B to complete the display. Then, by setting the control register to switch to another state, VRAM_A is used to complete the display, and VRAM_B is rewritten to keep the data of the two video memories the same. In this way, the display will not be affected when the system reads/writes the video memory. At the same time, the VRAM switching control circuit can be set to three video memory access modes: only high 8 bits, only low 8 bits, and 16 bits, so as to achieve fast video memory access and background overlay display functions.
The PAL video timing generator generates the clock, line field synchronization and blanking signals required for display, and provides them to the VRAM address generator submodule to form the address for addressing the external video memory. The memory resources inside the FPGA are instantiated as a 128K×4b ROM, and then the signal of 1 frame time length (40 ms) is designed into a .coe format file as the initialization data of the ROM.
The VRAM address generator generates the address required for reading the video memory according to the line, field synchronization and blanking signals given by the PAL video timing generator, and is synchronized with the PAL signal timing.
The function of the color lookup table is to convert the video image data read from the video memory into a 24-bit RGB color digital video after table lookup processing and provide it to the D/A converter to output to the display for display. The lookup table has a total of 512 units, which are divided into two parts, 0 to 255 for the first table and 256 to 511 for the second table. The digital video output from the video memory is converted either through the first table or through the second table, but not at the same time. When the upper 8 bits of the digital video are all 0, the lower 8 bits will be used to index the first table. When the upper 8 bits are not all 0, the upper 8 bits will be used to index the second table. In this way, the system can flexibly set and modify the content of the color lookup table by software to achieve a variety of layered and superimposed color display methods.

3 Application of SoPC technology in design
The development adopts Xilinx's EDK (Embedded Development Kit) and ISE tool software. The EDK toolkit integrates hardware platform generator (Platgen), software platform generator (Libgen), simulation model generator (Simgen), software compiler (Mb-gcc/ppc-gcc) and software debugging tool (Mb-gdb/ppc-gdb). Through the integrated development environment XPS, users can call all the above tools to complete the entire process of embedded system development. The
configuration level of configurable embedded systems includes processor configuration: such as instruction or data buffer configuration, coprocessor or hardware accelerator; system configuration: such as I/O peripheral selection, customization, DMA selection, memory peripheral selection, customization, etc.; user-specific peripherals and circuits: design the dedicated circuit into a user-defined IP Core, and then add calls to the system to implement it. The user-defined IP Core requires that it must be designed with HDL and meet the specifications of the on-chip bus interface and EDK project, such as a special directory structure and processor peripheral definition file (.MPD), peripheral analysis definition file (.PAO), etc. If the customized IP Core needs to have software driver, the design must also fully comply with the corresponding bus bottom driver interface specification. In short, the application of SoPC technology in the design of interface modules has the following advantages: since interface modules are often small embedded computer systems that implement special functions, the system memory can be integrated into the FPGA under the premise that the chip RAM resources can meet the design requirements of the system, which greatly reduces the size and power consumption and the number of chips; hardware design changes can be achieved by reconfiguring the FPGA device, increasing design flexibility and reducing design risks.

4 Conclusion
Due to the continuous enrichment of the types of communication interfaces and IP Cores integrated in FPGA, it has become possible to use SoPC technology for embedded system design in more application fields. This multifunctional interface module has been successfully applied to actual products, replacing the previous three separate interface modules, greatly reducing the size and power consumption, improving the performance while also improving the reliability of the system, and providing a development direction for the design of smaller and more powerful radar interface modules.