A low power consumption and high PSRR reference voltage source

Generally, the reference circuit based on self-bias , because the MOS tube works in the saturation region, its working current is generally in the microampere level. Although it can be applied to most consumer electronic chips , it cannot meet the design requirements for some special applications, such as rechargeable battery protection chips. Therefore, reducing the current of the reference circuit becomes the key to the low power consumption design of the chip. In order to reduce the static current of the circuit, the reference and bias circuit here adopts a combination of enhancement tube and depletion tube. For enhancement MOS tube, the threshold voltage decreases with the increase of temperature; for depletion MOS tube, the threshold voltage is negative, and its threshold voltage temperature coefficient is opposite to that of enhancement. A high-precision reference voltage is generated by using the negative temperature coefficient of the threshold voltage of the enhancement MOS tube and the positive temperature coefficient of the threshold voltage of the depletion tube.

1 Structure and working principle of reference voltage source

Figure 1 is an equivalent structure diagram of the reference voltage source. Among them, M4 is a consumption tube and M6 is an enhancement tube. As can be seen from Figure 1, after the gate and source of M4 are connected, the current flowing through the tube is:

Since the threshold voltage of the NMOS power transistor is negative and has a negative temperature coefficient, it can be seen from formula (1) that the power transistor current increases with the increase of temperature. This current is the current passing through the enhancement tube M6. From Figure 1, it can be seen that the reference voltage is:

Since the threshold voltage of the enhancement tube M6 has a negative temperature coefficient, and the current passing through the tube has a positive temperature coefficient, a relatively constant reference voltage can be obtained at room temperature by properly setting the width-to-length ratio of M4 and M6.

This kind of reference voltage source has the following advantages:

(1) It can generate a lower reference voltage. Compared with the general 1.2 V reference voltage, the circuit structure shown in Figure 1 can generate a lower reference voltage. Especially when the threshold of the NMOS tube of the selected process is small and the width-to-length ratio of the power consumption is small, the reference voltage is only a few tenths of a volt, which has a great advantage in low-voltage power supply chips.

(2) The circuit has a very small static current. The gate and source of the M4 tube are connected to act as a constant current source. Since the length of the tube is set to be large, the corresponding equivalent resistance is very large, and the static current flowing through is very small, generally only a few hundred nanoamperes.

(3) No additional startup circuit is required. A depletion-type transistor is a normally-on transistor. It will only turn off when the voltage applied to the gate exceeds its threshold voltage. The gate voltage of the M4 transistor is always 0, and the M6 ​​transistor is a diode connection. Therefore, after the system is powered on, there must be a DC path from the power supply to the ground, so there is no need for an additional startup circuit to help the system get rid of the degenerate state of quiescent current of 0.

2 Improved circuit structure and principle

The reference voltage source shown in FIG1 has the advantages of small quiescent current and no need for an additional startup circuit, but its power supply rejection ratio characteristic is not very good. In order to obtain a better power supply rejection characteristic, the reference unit of FIG1 can be cascaded, as shown in FIG2.

M1, M2, M4 are consumption tubes, M5, M6 are enhancement tubes. Among them, M1 and M5 are the first-stage circuit, M2, M4, M6 are the second-stage circuit, and the correlation between the first-stage and second-stage circuits is not large. By designing the width-to-length ratio of M1 and M5 tubes, a bias voltage smaller than the reference can be obtained. At the same time, the output is connected to the gate of M2 tube in the second-stage circuit of the reference power supply, which weakens the change of this point with the power supply voltage, thereby effectively improving the power supply rejection characteristics of the reference output.

This circuit uses CSMC's 0.6/μm process and uses a 49-level model for simulation, and the following results are obtained:

(1) Temperature coefficient. The simulation is performed under the conditions of input voltage 4.0 V and temperature of -40 to +100°C. From Figure 3, it can be seen that the reference voltage changes from 0.963 32 V at -40°C to 0.962 35 V at 30°C. Therefore, the temperature coefficient of the reference is (ppm/°C):

(2) Power supply rejection ratio of reference voltage . The power supply rejection ratio of reference voltage is shown in Figure 4.

It can be seen from Figures 4 and 5 that if M2 is not added, the PSRR at low frequency is only -90 dB, and at high frequency it is about -75 dB, and the power supply rejection ratio is not very good; if M2 tube is added, the PSRR at low frequency is -120 dB, and it can also be controlled within -90 dB at high frequency, and the power supply rejection ratio is greatly improved.

(3) Linear regulation of the reference voltage. Figure 6 shows the linear regulation characteristic curve of the reference voltage. It can be seen from Figure 6 that the linear regulation of the reference voltage decreases with the increase of temperature. At 25°C, the reference voltage changes from 1.027952 V corresponding to the input voltage of 2.5 V to 1.027982 V corresponding to the input voltage of 5.5 V. Its linear regulation is:

3 Conclusion

This paper analyzes and introduces a design scheme of a low-power reference voltage source circuit. The maximum power consumption of this circuit is less than 1μW, and the temperature coefficient is 21 ppm/℃. At the same time, due to the simple circuit structure and easy integration, it has been used in battery charging protection chips .