Improved interleaved DC/DC converters

Interleaved DC/DC converter topologies allow for more efficient designs than conventional parallel output stage transistors, and there is still room for improvement. In interleaved operation, many tiny converter cells (or phases) are placed in parallel. Ideally, active phase shift control circuits distribute power evenly to each phase, and this approach can eliminate current ripple at the output and increase the effective ripple frequency, thereby reducing the output filter capacitor requirements. Interleaving can also significantly reduce input inductor and capacitor requirements. However,
this approach has several disadvantages. One disadvantage is that there is a trade-off between the converter's full load efficiency and light load efficiency. With transistor stages connected in parallel, conduction losses are reduced, but switching losses are increased. At full load, conduction losses dominate and there is no problem. But at light load, the opposite is true, and switching losses dominate. In addition, current sharing between phases is also a troublesome issue, which is generally handled by active control circuits (without this circuit, the mismatch of tiny devices between parallel phases will cause huge phase current imbalances), and some methods are better than others.

Figure 1: Two-phase interleaved two-switch forward converter

Digital power management can more effectively address these issues by implementing complex control algorithms and having data bus capabilities. Below we will apply this technique to a two-phase interleaved two-switch forward converter for real-time optimization.
Improving Efficiency
A. Light vs. Heavy Loads
The total energy loss in a switching power converter is the sum of the conduction loss Pcond and the switching loss Psw. Given the output current Iout and the switching frequency fs, the switching loss is (Equation 1):
Psw = Psw1 + Psw2 = ksw1 • Iout • fs + ksw2 • fs
Where ksw1 and ksw2 are device-dependent switching loss coefficients. Generally speaking, the larger the transistor size, the higher the ksw1 and ksw2.
Ignoring the inductor current ripple, the conduction loss on the path resistance Rpath is (Equation 2):
Pcond = Iout2 • Rpath
Using interleaved phases in parallel can reduce the path resistance, thereby improving the efficiency at heavy loads. However, the power loss at light loads is dominated by switching losses. As ksw1 and ksw2 increase with more phases, interleaving significantly reduces the light load efficiency. Therefore, compared with a single-phase converter, an interleaved multiphase converter has higher heavy-load efficiency, but lower light-load efficiency. The converter efficiency is (Equation 3):

For a single-phase converter, the power conversion efficiency is 0 at no load because the switching loss part Psw2 always exists. As the output current increases, Psw2 becomes negligible, and the efficiency increases accordingly. The denominator in Equation 3 is a second-order polynomial, while the numerator is only first-order, so after the output current passes the optimal point, the efficiency starts to decrease again. For a two-phase converter, the output current at the efficiency optimal point is twice that of a single-phase converter. Therefore, the more phases, the higher the heavy-load efficiency, but the lower the light-load efficiency.
Previously, it was believed that only full-load efficiency was important. However, today, power converters are more often powered by light loads than by heavy loads. With the increasing demand for energy conservation, high light-load efficiency is critical for power supplies. Therefore, designers want to use intelligent interleaving controllers to achieve high efficiency operation at all loads.
B. Real-time efficiency optimization by controlling the number of phases
The above power loss analysis shows that it is not appropriate to have two parallel phases operating at light load at the same time. If one phase is turned off, the situation changes dramatically. Conduction losses increase, but switching losses decrease, resulting in higher light-load efficiency. The key is to ensure that the number of phases is optimized in real time.
Figure 2 shows experimental waveforms of a two-phase interleaved two-switch forward converter, in this case controlled by the ADP1043 digital controller from Analog Devices. When the total load current drops below a certain threshold, the second phase is disabled. As shown in Figure 3, light-load efficiency is improved when one phase is turned off. The difference in light-load efficiency between and without phase optimization control can be as high as 15%.

Figure 2: Automatic phase shutoff using ADP1043
B. Real-time efficiency optimization through DCM operation
As can be seen from Figure 3, for very light loads, even single-phase operation can significantly reduce efficiency. One reason is that the converter uses synchronous rectifiers on the secondary side (Figure 1), and when the output current level is lower than the current ripple, reverse current flows through the output inductor, and this circulating current causes conduction losses. To improve efficiency, one solution is to turn off all secondary-side synchronous rectifiers and let the body diodes or parallel diodes (Schottky diodes in most cases) run freely. When the load is low enough, the converter operates in discontinuous current mode (DCM) to avoid the problem of circulating current.

Figure 3: High efficiency interleaved two-switch forward converter

With this scheme, the converter efficiency is 5% higher than that of continuous current mode (CCM). In addition, shutting down one phase at light load can further improve efficiency across the entire application load range.
D. Other Considerations In addition to taking the above measures to optimize real-time efficiency, designers must carefully consider the design of the power stage and controller. The power stage, sensing network, and feedback control circuit have inherent propagation delays, so during fast load step-up transients, the system must maintain the output voltage of the first phase to stabilize before starting the second phase. In addition, the system should be able to handle full power for a short period of time. The transistor selection should be based on this thermally sensitive condition. In addition, the magnetic design should avoid saturation of the system at higher output currents.
As for the controller, the feedback compensator needs to be adjusted for different operating modes because the power stage transfer function changes with the number of phases and CCM/DCM conditions. This requires intelligent management from the controller, which is difficult for traditional controllers to handle. In addition, digital power management controllers can automatically detect load conditions and smoothly switch to the appropriate converter mode. Phase
-by-phase current-sharing interleaving operation itself does not ensure even current distribution. Since the paralleled phases share the same voltage feedback, there is no error due to reference voltage mismatch. Therefore, load imbalance is related to device tolerance, drive imbalance and timing errors.
Current imbalance causes thermal and device stress. Transistors and magnetic devices must be designed with insurance against possible overstress conditions. In addition, efficiency will be affected. For example, if the total current of the interleaved forward converter is 30A and the two phases provide 10A and 20A respectively, the efficiency drop due to this factor is close to 1%.
There are two control schemes that can be used to achieve current sharing among the phases: inner loop current sharing and dual loop current sharing. Inner loop current sharing is essentially current mode control. The output of the voltage compensator is used as a current sharing bus to provide the output current reference for all phases. Within the voltage loop, the current sharing loop design is not limited by the voltage bandwidth, and the current sharing response can even be faster than the voltage loop. However, when designing the outer voltage loop, the impact of the inner loop must be considered. If the inner loop is faster, the voltage regulation function of the outer loop may be weakened.
In dual-loop operation, the voltage regulation loop and the current sharing loop are connected in parallel. Each phase has a dedicated current sharing compensator to ensure that its current follows the current sharing bus, which can be the average current of the parallel phases or the highest phase current. The output of the current sharing loop for each phase is summed with the common voltage compensator output to generate the duty cycle signal for that phase. In this way, both the current sharing controller and the voltage regulation controller affect the generation of the duty cycle signal. When using this control structure, each loop can be designed flexibly, and the designer does not have to worry too much about the interaction between the current sharing loop and the voltage regulation loop.
Regardless of the current sharing scheme used, the current of each phase must be sensed for active control. The traditional approach is to use a current sensing scheme for each phase. Current sensing is generally used for protection purposes, and this technique increases the cost of the interleaved converter.
In order to use one input to sense the current of two phases, the controller must separate the current of each phase. In interleaved forward operation, the duty cycle of the main switch is always less than 50% to avoid transformer saturation. With 180 degrees of phase shift, there is no signal overlap in the main switch current sensing. Therefore, digital control allows the sense signal to be distributed to align with the duty cycle signal of each phase. This allows the current of each phase to be clearly distinguished using only one current sensing circuit. The controller monitors the current flowing in each phase, stores this information, and compensates the drive signal to ensure current sharing.
Figure 4 shows an example of an interleaved forward converter using the ADP1043 controller to implement the above scheme. It is obvious that since the duty cycle is less than 50%, the controller can determine the current of each phase using a common current sense point. Without current sharing control, the current of the second phase is almost twice that of the first phase. With current sharing control enabled, the current difference between the two phases is greatly reduced to 5%.

Figure 4. Effect of two-phase current sharing control: (top) current sharing control enabled; (bottom) current sharing control disabled.
In summary, interleaved operation provides advantages over single-phase design. The benefits of interleaved operation can be further extended using digital power management. Digital control also enables a simple current sharing scheme.
About the Author
Yang Qiu (yang.qiu@analog.com) is a senior applications engineer at Analog Devices in San Jose, California. He received his bachelor’s and master’s degrees in electrical engineering from Tsinghua University in Beijing, China, and his Ph.D. from the Center for Power Electronics Systems (CPES) at Virginia Tech in Blacksburg, Virginia.