Effect of stray inductance on high-efficiency IGBT inverter design

IGBT technology cannot lag behind application requirements. Therefore, Infineon has launched the latest generation of IGBT chips to meet the needs of specific applications. The switching speed and softness requirements related to the application power or the respective rated current level of current inverter designs are the main driving force for the optimization of these different types of devices. These types include T4 chips with fast switching characteristics, P4 chips with soft switching characteristics and E4 chips with switching speeds between T4 and P4.

Table 1 briefly introduces the three trade-off points of IGBT and gives suggestions for the corresponding current ranges.

Table 1: Brief introduction of Infineon 1200V IGBT.

Dynamic losses of IGBT and diode

To study and compare the switching losses and softness of the three different chips at stray inductances ranging from 23nH to 100nH, a module close to the reasonable limits for optimal use of the T4 chip was selected. Therefore, a 300A half-bridge configuration in a common 62mm package was chosen as a platform, and the module was equipped with the three IGBT chips.

All three modules use the same high-efficiency emitter-controlled diode and gate drive setup. Figure 1 shows the experimental setup.

Figure 1: Test setup: To test the reverse recovery characteristics of the freewheeling diode, the high-side IGBT is driven and the load inductor is changed to be connected in parallel with the low-side diode.

Figure 2 shows the effect of two different stray inductances on the turn-on waveform of a 300A half-bridge equipped with IGBT-T4.

Figure 2: Turn-on characteristics of T4: The upper figure shows the loss/time curve for two inductors (Ls=23nH and Ls=100nH); the lower figure shows the voltage and current curves.

When the current increases, the higher stray inductance Ls not only increases the inductive voltage drop at the device terminal (Δu=-L*di/dt), but also affects the current rise speed di/dt itself. Although the parasitic inductance slows down the conduction speed, the conduction loss is greatly reduced.

In this example, the losses in the initial switching phase (see time stamp a in Figure 2) decrease from 30.4mW to 12mW as the stray inductance increases.

The second stage of the switching event is characterized by a reverse recovery current peak in the diode and a further drop in the IGBT voltage. The increase in parasitic inductance leads to a delay in the reverse recovery current peak and an increase in the switching losses in the second stage.

Therefore, the increase in parasitic inductance can significantly reduce the turn-on losses for the entire switching event. In this example, the losses are reduced from 40mW to 23.2mW.

It is well known that although di/dt can reduce the voltage of IGBT during turn-on, it will also increase the voltage overshoot of IGBT during turn-off. Therefore, the increase of DC bus inductance will increase the turn-off loss. As shown in Figure 3, the turn-off switching event can be divided into two stages.

Figure 3: Turn-off characteristics of a low-power IGBT: The upper figure shows the loss/time curve (solid line: L=23nH, dotted line: L=100nH); the lower figure shows the voltage and current curves.

The current waveforms for the small and large inductance settings cross at timestamp b. In the first switching phase until the crossover point b, the increased overvoltage with the large inductance setting increases the losses to 36.3 mJ, while the losses for the small inductance setting are 30.8 mJ. However, after point b, the large inductance setting produces a shorter current tail, so that the losses in this phase are 1.8 mJ lower than those for the small inductance setting. This result is mainly influenced by the reduced current tail, which reaches the 10% value more quickly.

As the stray inductance increases, the turn-on loss of the IGBT decreases, while the diode loss increases (as shown in Figure 4). Figure 4 shows the comparison of the diode recovery characteristics under small and large inductance conditions.

Figure 4: Diode recovery characteristics: The upper figure shows the loss/time curve for two inductors (solid line: L=23nH, dashed line: L=100nH), and the lower figure shows the voltage and current curves.

It is obvious that the reduced di/dt of the IGBT has almost no effect on the losses in the beginning of the diode commutation phase, as the diode voltage remains around zero. After the reverse recovery peak current, the diode voltage rise caused by the larger stray inductance dominates and causes additional losses. The intersection point c can be seen again in the diode tail current for the small and large inductance settings. The higher overvoltage increases the losses before point c from 10.1mJ to 19.6mJ. As in the case of the IGBT, the increased dynamic overvoltage leads to a reduction in the tail current after point c, and the loss balance of the large inductance setting is optimized by 4.4mJ. In summary, the first switching phase is dominant, and the diode losses increase by 20% from 24.6mJ to 29.7mJ with the increase in inductance.

Table 2: Tradeoffs for Infineon IGBTs: turn-off losses at the same stray inductance and softness.

Total dynamic loss of experimental results

Although the combination of di/dt and parasitic inductance can reduce the voltage of the IGBT during the turn-on process, it will increase the voltage overshoot of the IGBT during the turn-off process. Comparing the turn-on and turn-off processes, it is not difficult to see that the reduction in turn-on loss is much greater than the increase in turn-off loss when the parasitic inductance is large.

This trend can be easily understood if one considers that the turn-off di/dt of the latest trench-gate field-stop IGBTs is essentially governed by the device dynamics and is approximately half the turn-on di/dt.

In Figure 5, the IGBT turn-on loss, turn-off loss and diode commutation loss are compared with the parasitic DC bus stray inductance of the three IGBTs.

Figure 5: Switching losses as a function of stray inductance Ls. Increasing the inductance will reduce the IGBT turn-on losses (left); the IGBT turn-off losses (right) and the freewheeling diode turn-off losses will increase with increasing inductance.

Softness and current surge characteristics of IGBT and diode

It has been shown above that parasitic inductances can be beneficial for the overall loss balance. However, stray inductances can also lead to oscillations, for example caused by sudden current changes, which can result in device usage restrictions due to EMI or overvoltage limitations. All measurements presented so far were performed at a loss-critical junction temperature of Tvj = 150°C. Sudden current changes are even more critical at low temperatures, since carrier injection into the device decreases with decreasing temperature and significantly reduces the charge available for smoothing the tail current. Therefore, Figure 6 compares the IGBT turn-off of the three chips at rated current at 25°C and 600V DC link voltage. The DC link inductance is used as a parameter.

Figure 6: Switching curves as a function of the stray inductance LSd of three IGBTs: T4 (left), E4 (center), P4 (right); top graph: gate voltage; bottom graph: current and voltage curves.

In the given example, T4 becomes stiff and oscillations start to occur when the stray inductance is about 55nH. Under the same conditions, E4 remains soft until the DC link inductance reaches about 80nH. For the P4 chip optimized for high power, it remains soft in the observed inductance range (20nH…100nH). This observation is not surprising, since the IGBT is designed for high power modules with rated currents up to 3600A.

While the current mutation tendency of IGBTs is usually most obvious at low temperatures and high currents, the freewheeling diode softness is usually most critical at low temperatures and low currents. This depends on several factors: Because the diode is a carrier lifetime optimized device, the plasma density is lowest at low currents, so the tail charge weakens with decreasing current levels. In addition, the switching IGBT that forces the diode to commutate is usually switched faster at low current levels. Finally, the diode overvoltage has nothing to do with the switching current, but is caused by the negative slope of the diode's reverse recovery current peak, which is also steepest at low currents and low temperatures.

Due to the effects of fast switching transients (du/dt and reverse recovery di/dt), DC link oscillations can be easily triggered at low current levels, even without a sudden change in diode current. Figure 7 presents the reverse recovery characteristics of the freewheeling diode under different stray inductance conditions.

Figure 7: Recovery performance of the diode at room temperature and 1/10In (curves for different LS).

In this case, low stray inductance can produce a higher resonant frequency and help suppress this oscillation. Of course, if the large stray inductance causes the diode to have a real current jump, the situation will be worse. For EMI considerations, this will limit the use of higher stray inductance.

Conclusion

When working under the same conditions, the design optimization of IGBT to improve softness requirements will come at the cost of increased switching losses.

In addition to switching losses, turn-on and turn-off speeds, current mutations and oscillations (EMI) are becoming more and more important. Parasitic stray inductance plays an important role in the DC bus resonant frequency and diode current mutations. At least from an EMI perspective, diode current mutations will limit the reduction of turn-on losses by increasing stray inductance or increasing the IGBT turn-on speed.

Therefore, it is expected that different models of IGBT optimized products will be launched in the future. On the other hand, considering that the DC bus inductance is a free parameter in the inverter design, this will help to further optimize the loss.

Importantly, to ensure the use of fast switching devices (such as T4 chips), the DC bus design must be further optimized. In energy-efficient design, the lower the inductance, the better is a simple principle.