Design of a white light LED driver chip based on current control mode

The huge market and development potential of current consumer electronic products have led to the rapid development of low -power , low-power, high-efficiency, small-size, and light-weight DC/DC converters for battery-powered portable products. For many electronic systems used in portable products, such as color LCD displays and mobile phone backlight screens, DC/DC is an ideal power conversion device.

This paper designs a current-controlled PFM Boost DC-DC switch converter chip based on 2μm 15V bipolar process. The loss of external feedback resistor is reduced by using low feedback resistance technology, and load current feedback technology is used to adjust the system duty cycle to reduce the output voltage and current ripple coefficient when the system is in steady state. The chip adopts Fixed-On-Time control mode. When the entire system is in steady state, it is in the discontinuous conduction mode (DCM) of Boost PFM, and this working mode has natural stability.

1. Circuit system structure design

The system adopts the typical current-controlled PFM Boost DC-DC converter topology as shown in Figure 1. The dotted box is the chip principle block diagram, and the outside of the box is the peripheral device connection diagram. Among them, STDN is the enable terminal of the chip. When the level is low, the entire chip is turned off to reduce static power consumption; SENSE is the output voltage feedback sampling terminal; VFB is the load current feedback sampling terminal; DRIVE is the external power switch control terminal; the reference voltage generates the reference voltage VRA2 of the A2 comparator through the resistor voltage divider; the reference voltage of the A1 comparator is VRA1; A1 and A2 control a monostable circuit with a transient steady state of 1.7μs through a two-terminal NAND gate; the output stage DRIVE drives the external power tube QT.

The system will work in two states: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). VIN is powered on, STDN is set to a high level, and the reference source is the comparison reference voltage VRA2 provided by the A2 comparator. Since the system has just started, A1 and A2 output high levels, the monostable circuit is not triggered, the output is high, and the external power tube QT is turned on. When VSENSE>VRA1, A1 outputs a low level, the monostable circuit is triggered, the DRIVE voltage is quickly pulled down, and the external C2 begins to charge. Before the voltage across RS2 reaches the A2 comparison reference voltage, the system will repeat the above process and the system will work in continuous conduction mode. When the voltage across RS2 exceeds the A2 comparison voltage VRA2, the A2 comparator outputs a low level, the monostable circuit is triggered, and the external power tube is turned off. From this point on, L charges C2 within 1.7μs. When L is fully discharged, C2 begins to discharge, causing the voltage across RS2 to still exceed the A2 comparison voltage. A2 outputs a low level, the monostable circuit continues to output a low level, the external power tube continues to be in the off state, and the system works in the discontinuous conduction mode. The system starts the boost in the continuous conduction mode, and the system is in the discontinuous conduction mode after entering the steady state.

2. Circuit principle and design

2.1 Switch current limiting control circuit

The loop composed of A1 comparator, monostable trigger, driver amplifier and external switch tube in Figure 1 is a switch current limiting control circuit. Assume that the monostable trigger outputs a high-voltage stable state, the external power tube QT is turned on, the diode D is turned off, and the current in the inductor L rises linearly. When the inductor current is small, the voltage drop on the current limiting resistor RS1 is less than 30mV, the A1 comparator outputs a low level, and the monostable trigger cannot be triggered to flip; when the inductor current rises to the current limit Ipk, the voltage drop on the resistor RS1 reaches VRA1, the A1 comparator output flips, and the output low level is controlled by the NAND gate to enter the temporary stable state of the monostable circuit, and the external power tube QT is turned off. Since the inductor current must be continuous, the induced electromotive force of the inductor L is negative on the left and positive on the right, the diode D is turned on, the inductor L begins to charge C2, and the output voltage VOUT rises. This process will last for 1.7μs until the temporary stable state ends, the monostable trigger returns to the high-voltage stable state, and QT repeats the above switching process again until VOUT finally reaches the rated output voltage.

Figure 2 is the A1 comparator circuit, BIAS is the bias terminal, VA1 is the output terminal, VS is the positive input terminal, and SENSE is the negative input terminal, which is the external inductor current Ipk detection terminal. Since Q10, Q11, and Q12 have the same bias, they provide the same bias current. Q10, Q13, and RS constitute the A1 comparator positive input branch. Since the voltages of VCC and VBIAS are constants, Q13 is connected by a diode, and the voltage at point A is VBE13+VS; since Q13 and Q14 are both NPN tubes, their VBE threshold voltages are the same. When VSENSE>VBE13+VS-VT(be), Q14 is cut off, point B rises to a high level, Q15 is turned on, VA1 outputs a low level, and the monostable circuit is triggered by controlling the NAND gate, the external power tube is turned off, VSENSE drops rapidly to 0, Q14 is turned on, point B is pulled to a low level, Q15 is turned off, and VA1 outputs a high level. At this time, the control signal is shielded by the NAND gate and the monostable circuit is not triggered. The circuit enters a 1.7μs transient state, waiting for the discharge of the external inductor L to end.

Since the main power loss of the system peripheral circuit comes from the parasitic series resistance of the feedback resistor RS1 and the inductor L, the power consumption of the system peripheral devices can be reduced by low feedback resistance technology. That is, by adjusting RS, a comparison reference voltage VRA1 (about 30mV) as small as possible can be provided. For the inductor:

When VRA1 is reduced, for the same inductance Ipk, the RS1 resistance can be effectively reduced, thereby reducing the power consumption of system peripheral devices.

2.2 Load current feedback circuit

In Figure 1, the loop composed of inductor L, diode D, load, detection resistor RS2, and A2 comparator is the load current feedback circuit. The VFB terminal is the reverse output terminal of A2 comparator, that is, the load current detection terminal. When the system enters the transient state, the inductor L supplies power to the capacitor C2 and the load through the diode D. At this time, the current supplied by the inductor L to the load is Ipk. At this time, the detection voltage VFB at the VFB terminal reaches a maximum of Ipk×RS2, which is greater than the positive reference voltage VRA2 of the A2 comparator. The A2 comparator outputs a low level and controls the monostable trigger through the NAND gate to turn off the external power tube. At this time, the system has entered the transient state, and the external power tube is already in the off state. The A2 comparator will continue to trigger the monostable. As the inductor current IL decreases, the voltage across the capacitor C2 gradually rises. When the external inductor current IL satisfies formula (2):

At this time, capacitor C2 starts to supply power to the load. When the inductor current IL drops to 0, the system enters the inductor current discontinuous mode. At this time, only capacitor C2 supplies power to the load. When the load current ILoad is less than IL0, the A2 comparator outputs a high level, and its control signal is shielded by the NAND gate, and the monostable circuit is not triggered. At this time, the external power tube is turned on and starts to charge the inductor L.

The reference circuit and A2 comparator circuit are shown in Figure 3, with the bandgap reference circuit on the left and the A2 comparator on the right. Q1~Q5 and R1~R3 ​​form a bandgap structure to generate a bandgap reference voltage VREF, which is divided by resistors to generate a comparator reference voltage VRA2. The difference between the VBE of Q4 and Q5 is:

Among them, AE4 and AE5 are the emitter area of ​​transistors Q4 and Q5, and the ratio is N:1. The reference voltage is:

Q6~Q9 and R6 form the A2 comparator, BIAS is the bias voltage, point D is the positive input terminal, VFB is the negative input terminal, and VRA2 is the output terminal of the A2 comparator. The A2 comparator mainly adjusts the duty cycle according to the load current to reduce the load current fluctuation.

As shown in Figure 3, the positive terminal reference voltage is:

Q6 and Q7 have the same bias, Q8 is connected in diode mode, when the external power tube is turned on, VFB

Q9 is turned off, VA2 outputs a high level, and the monostable is not triggered. When VFB>VRA2, Q9 is turned on, VA2 outputs a low level, triggering the monostable and turning off the external power tube.

3. Simulation results

The circuit design is carried out using 2μm 15V bipolar process, and the connections of the circuit modules and peripheral components are shown in Figure 4. The values ​​of the peripheral components are: L=22μH, RS1=40mΩ, RS2=15Ω, C1=2.2μF, C2=2.2μF. HPS ic e circuit simulation software is used to simulate and verify the circuit.

Under the typical operating conditions of the system (VIN=3V, T=25℃, VOUT=10.8V), the transient simulation output waveforms of each terminal of the system are shown in Figure 4 (under typical conditions, the system only takes about 200μs to reach a stable output voltage). Table 1 shows the simulation results of electrical characteristics under typical operating conditions.

4. Chip layout design

Compared with CMOS process, bipolar process has the advantages of low noise, high speed, strong driving capability and high precision. The chip is designed with 2μm bipolar process. Due to the simple circuit structure and fewer devices, the layout area is 0.67mm×1.28mm.

This paper designs a white light LED driver chip for color LCD backlighting . The PFM control mode low feedback resistance technology and load current feedback technology are used to achieve the design goal of low power consumption constant current output. Based on 2μm bipolar process simulation verification, in a typical application of 20mA, the current regulation rate reaches 0.02mA/V and the efficiency is 80.1%. The chip can work stably at a power supply voltage of 8V, and the maximum quiescent current is 152μA. The chip has the advantages of low power consumption, small voltage and current ripple coefficient, and low cost.