Design of a large LED screen control system based on MCU+FPGA

If you take a look at the current market, you will find that most small and medium-sized LED display systems use traditional single-chip microcomputers as the main control chip. However, single-chip microcomputers with less internal resources and slower running speeds are difficult to meet the needs of large-screen LED displays, because the system requires large data transmission volume and fast scanning speed. Using FPGA as a controller, on the one hand, FPGA uses software programming to implement hardware functions, which can effectively improve the running speed; on the other hand, it has rich pin resources and strong scalability. Therefore, a single-chip FPGA and a simple peripheral circuit can realize the control of a large-screen LED display, which has the advantages of high integration, good stability, flexible design and high efficiency.

1 System overall structure

The LED large screen display system consists of a host computer (PC), a single-chip microcomputer system, an FPGA controller, and a row and column drive circuit of the LED display, as shown in Figure 1. The host computer is responsible for the collection and transmission of Chinese characters and other data. The single-chip microcomputer system and the host computer use asynchronous serial communication to obtain the graphic dot matrix data to be displayed from the host computer through the serial port, and store it in the EEPROM memory. After that, the display data in the memory is restored to the LED display through the FPGA controller. The scanning control circuit uses the programmable logic chip Cyclone EP1C6, which is implemented by VHDL language programming, adopts 1/16 scanning mode, and the refresh frequency is above 60 Hz. This article focuses on the FPGA control module of the 256×1024 monochrome graphic display.

Figure 1 System overall structure diagram

2 Basic working principle of LED display

For large-screen LED displays, the column display data usually adopts serial transmission mode, and the row adopts 1/16 scanning mode. Figure 2 shows the basic structure of the 16×32 dot matrix screen unit module. The column drive circuit is composed of 4 74HC595 cascades. Under the action of the shift pulse SRCLK, the serial data is input one by one from the data port SER of the 74HC595. When all 32 columns of data in a row are transmitted, the latch signal RCLK is output and the row signal Y0 is selected, then the data of each column of the first row can be displayed as required. The remaining rows are displayed in the same way. After 16 rows of data are scanned once (that is, one cycle is completed), the next cycle of scanning starts from the first row. As long as the scanning cycle is less than 20 ms, the display screen will not flicker.

Figure 2 Basic structure of 16×32 dot matrix screen

The 256×1024 large screen display is composed of 16×32 16×32 dot matrix screens cascaded together. In order to shorten the signal transmission time from the control system to the screen, the display data is divided into 16 areas, each area is composed of 16×1024 dot matrix, and each row of data is 1024/8=128 bytes. The pixel signal of the display screen is transmitted and shifted from the right side to the left side of the LED display screen, and the data of the 16 partitions are stored in the same memory. The display data of one screen is 32 KB. To accurately read the data of 16 partitions, the read address of its memory consists of 16 bits. Since the data is only 32 KB, the maximum can be set to 0. The remaining 15-bit address is from high to low: row address (4 bits), column address (7 bits), partition address (4 bits). The decoding signal (Y0~Y15) of the 4-bit partition address is used as the latch pulse of the latch. In the 16 read address generation cycles, the first byte data of the 1st to 16th partitions are latched into the corresponding latches in turn, and then the 16 bytes of data are latched into 16 8-bit parallel-to-serial shift register groups at the rising edge of the shift latch signal. In the next 16 read address generation clock cycles, on the one hand, the parallel-to-serial shift register shifts the 8-bit data into serial output, and the shift clock is the frequency divided by two of the read address generation clock; on the other hand, the second byte data of the 16 partitions are read out and locked into the corresponding latches in turn. According to this rule, after all the first row data of all partitions are read out in turn, all the serial shift data are output at the rising edge of the data valid pulse signal to drive the LED display. Next, the data of the second row is shifted out, and the first row remains displayed during this period; after all the second row is shifted in, the second row is driven to display, and the third row is shifted in at the same time... According to this way of scanning each partition in rows, the scanning display of the entire LED large screen is completed.

3 Design of FPGA-based display controller

3.1 FPGA control module overall plan

As shown in Figure 3, the FPGA control module is mainly composed of a single-chip microcomputer and FPGA interface and a data read and write module, a read address generator, a decoder, a row address generator, a data latch group, a shift register group, a pulse generator and other modules.

Figure 3 Overall structure diagram of FPGA control module

The read address generator mainly generates the read address signal, which is sent to the MCU interface and the data read/write module to read the processed LED display data in the external SRAM1 or SRAM2, and send the data to the data latch group for latching in a partitioned manner. The latch outputs 16 partition data, and the serial data required by the display is obtained through the parallel-to-serial conversion of the shift register group, and sent to the LED display column drive circuit. The pulse generator provides the corresponding synchronous clock for each module, and the row address generator generates the corresponding row signal and sends it to the row drive circuit of the display.

3.2 MCU and FPGA interface and data reading and writing module

The structure of the single-chip microcomputer and FPGA interface and data read-write module is shown in Figure 4. After the single-chip microcomputer reads data from the EEPROM and processes it according to the display requirements, it sends the data to the data buffer SRAM1 or SRAM2 through the interface and data read-write module. In order to improve the data transmission speed and ensure the continuity of the display effect, the dual-body switching technology is used in the system to complete the data storage process. In other words, a dual SRAM storage structure is adopted, and two completely independent read and write address lines and data lines are switched in turn for reading and writing. When working, the FPGA only reads the displayed data from one of the two SRAMs at a specific time for display, and the other SRAM exchanges data with the MCU. The MCU will write new data and work alternately in turn to realize display modes such as left shift, up shift, and dual screen. If the displayed content does not change, that is, the data in one SRAM does not change, the MCU does not need to write data to the other SRAM.

Figure 4 MCU and FPGA interface and data read and write module structure diagram

Figure 5 Data read and write state transition diagram

This module is implemented using a VHDL finite state machine. The entire control is divided into four states, and its state transition diagram is shown in Figure 5. Its working process is as follows: the system is turned on and enters the initial state ST0. The write enable terminal E of the microcontroller is at a low level. The microcontroller reads data from the EEPROM and writes the data to SRAM1. At the same time, the FPGA reads the data in SRAM2. When the microcontroller writes a screen of data, E becomes a high level. When the FPGA finishes reading data from SRAM2 and the end signal READ_END is at a low level, it enters the ST1 state.

In the ST1 state, if there is no new data written, E remains at a high level, and the FPGA reads the data in SRAM1 for static display; only when the microcontroller's read-in control signal E is at a low level and READ_END is at a low level, it enters the ST2 state. In the ST2 state, the microcontroller writes the data into SRAM2, and the FPGA reads the data from SRAM1 at the same time. After the microcontroller data is written, E becomes a high level. When the FPGA finishes reading a screen of data, READ_END is a low level, and it enters the ST3 state. In the ST3 state, if there is no new data written, E is a high level, and the FPGA reads the data in SRAM2. When the microcontroller has new data written, E becomes a low level. When the FPGA finishes reading a screen of data, READ_END is a low level, and it re-enters the ST0 state. The writing and reading of data is completed through this cyclical alternating work, and its port program is as follows:

ENTITY WRITEREAD_SEL IS

PORT（

REST:IN STD_LOGIC;

CLK:IN STD_LOGIC;

E:IN STD_LOGIC;  MCU write mark

WR:IN STD_LOGIC; MCU write control signal

ADDR_WR: IN STD_LOGIC_VECTOR (15 DOWNTO 0); MCU write address signal

ADDR_RD: IN STD_LOGIC_VECTOR (15 DOWNTO 0);   Read address signal

DIN: IN STD_LOGIC_VECTOR (7 DOWNTO 0); MCU writes data

READ_END:IN STD_LOGIC; Read one screen of data and end the mark

D1, D2: BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0);   SRAM data

AD1, AD2: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);   SRAM address

WR1, WR2: OUT STD_LOGIC;   SRAM write control signal

OE1, OE2: OUT STD_LOGIC; SRAM read control signal

DOUT: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); Output data

END ENTITY WRITEREAD_SEL;

3.3 Read Address Generator

The read address generator mainly generates the read address signal of the external buffer SRAM1 (SRAM2), so that the system can correctly read the corresponding display data from the memory. Its highest address bit is 0, and the remaining addresses are 15-bit valid address signals of row address (hang[30]), column address (lie[60]), and partition address (qu[30]). 16 bytes of data in SRAM1 (SRAM2) are read out within 16 pulse cycles. Part of the VHDL source program is as follows:

ENTITY addressIS

PORT（

RDCLK:IN STD_LOGIC;   Read address clock signal

CLR,ADDR_EN:IN STD_LOGIC;   Clear and enable control signal

READ_END:OUT STD_LOGIC;   One screen data read complete signal

ADDR_RD: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));   The read address signal generated

END ENTITY address;

3.4 Decoder

The decoder module mainly generates 16 partition signals (low level is valid) to control 16 latches respectively, and latches the display data of the 16 partitions in the corresponding latches respectively.

3.5 Data latch group and shift register group module

The data latch group module consists of 16 8-bit latches to latch the data of 16 partitions. The shift register group module consists of 16 8-bit shift registers to convert the 8-bit parallel data in each latch into 16 serial data output simultaneously, drive the LED display, and realize the parallel-to-serial conversion of data.

The generated component symbol is shown in Figure 6. Among them, DATA_IN[70] is the 8-bit parallel data input of each partition, SCLK is the shift clock, CLR is the clear signal, LOAD is the data latch signal, CS[150] is the input signal of 16 partitions (connected to the output of the decoder), and DATA_OUT[150] is the 16-channel serial data output.

Figure 6 Parallel-to-serial conversion component symbol diagram

3.6 Pulse Generator

The system uses a 1/16 scanning method to divide the data into 16 partitions, and the data of the 16 partitions is transmitted simultaneously. Assuming that the refresh frequency is 60 Hz (that is, the period is 16.67 ms), the display time of each line is about 16.67 ms/16=1.04 ms. Each line has 1024 bits, so the shift pulse period is 1.04/1024=1.02 μs, that is, the shift frequency must be above 0.983 MHz to meet the requirements. Since the shift pulse is 2-divided by the clock of the data reading module, the system clock is at least 1.97 MHz. This system uses a 50 MHz clock source. Its timing diagram is shown in Figure 7.

Figure 7 Clock generation timing diagram

Among them, RDCLK is the FPGA data reading clock; SCLK is the serial output shift clock, which is 2 times the frequency of RDCLK; LOAD is the data latch signal, which generates a latch signal after reading a byte of data DATA in the 16 partitions each time, and the data is latched in the data latch group, whose clock is 16 times the frequency of RDCLK.

4 Simulation test of FPGA control module

Create a project in QuartusII 5.1 and create a schematic file. Connect the module component symbols generated by the single-chip microcomputer and FPGA interface and the data read and write module, read address generator, decoder, row address generator, data latch, shift register, pulse generator and other unit modules to form the logic diagram of the overall control module and simulate its function. The simulation result is shown in Figure 8. 16 bytes of data are read from the memory and 16 serial data are output through parallel-to-serial conversion. From the waveform analysis, the function is correct and the signals of each output port meet the timing requirements.

Figure 8 FPGA control module simulation diagram

5 Conclusion

FPGA is an online programmable chip that can be programmed differently according to different user requirements, shortening the system development cycle and saving hardware development costs. This article uses FPGA as the main chip to design a relatively complete large-screen LED monochrome graphic display control system. With the development of LED display technology, the combination of FPGA and ARM or DSP chips will surely be widely used in the field of dual-color display and color display.