Design and Application of MSK Modem Based on FPGA

Digital modems have been widely used in point-to-point data transmission. Conventional binary digital modems are based on analog carriers, and require analog signal sources when implementing circuits, which can be inconvenient for all-digital applications. This paper analyzes the characteristics of MSK (minimum shift keying) digital modulation signals, proposes a design method for an all-digital fixed data rate MSK modem, and uses VHDL language for module design and timing simulation. The hardware part implements the MSK digital modem on Altera's EP2C15AF256C8N FPGA, and is applied in the embedded measurement and control part of the Changzhou Science and Technology Key Project: Grain Storage Safety Network Intelligent Monitoring System . Actual measurements show that the digital MSK modem has the advantages of constant envelope, continuous phase, and high bandwidth utilization. In addition, the design efficiency is high when implemented on FPGA, and on-chip resources can be shared with other modules. It is a better solution for short-distance data communication in all-digital systems .

1 Carrier frequency and phase constant of digital MSK modulation

Minimum Frequency Shift Keying (MSK) is a special form of binary continuous phase FSK. Sometimes it is also called Fast Frequency Shift Keying (FFSK). MSK modulation can obtain orthogonal signals with the minimum modulation index (0.5). At the same time, MSK has a higher data transmission rate than 2PSK, and the out-of-band spectrum components decay faster than 2PSK.

MSK is a constant envelope continuous phase frequency modulation, and its signal expression is

MSK modulation must satisfy both the modulation index 0.5 and phase continuity conditions. From the MSK signal representation, we can see that in order to make the modulation index 0.5, the two frequencies of the MSK signal should be:

The above formula reflects the constraint relationship between the code element intervals before and after the MSK signal. The phase constant of the MSK signal at the kth code element is not only related to the value of the current code element, but also to the value and phase constant of the previous code element. In the case of a digital carrier, the above conditions are equivalent to selecting the phase of the current code element to be in phase or inverse phase according to the phase of the previous code element to ensure the phase continuity of the digital MSK signal.

2 Digital MSK Modem FPGA Module Implementation

The MSK modulator module implemented with FPGA is shown in Figure 1.

Figure 1 MSK modulator module

The pre-divider and the "0" and "1" code dividers in the figure form a carrier generator, which generates digital carriers of "0" code and "1" code respectively under the control of the input code sequence synchronization signal. In order to facilitate design and adjustment, the pre-divider sets a 2-level frequency division circuit, and the frequency division coefficients are D1 and D2 respectively. Considering the frequency division efficiency, the product of D1 and D2 should be the largest common factor of the total frequency division coefficient.

The frequency division coefficients C1 and C2 of the "0" code and "1" code dividers must meet the condition of modulation index 0.5. The input modulation signal digital sequence controls the 2-to-1 multiplexer to select the digital carrier corresponding to the "0" and "1" code elements in the input code stream. The phase detection module, the second-stage 2-to-1 multiplexer, the code length divider and the inverter form a continuous phase forming circuit. When the digital carrier of the "0" and "1" code elements is determined in the previous step, the number of carrier cycles of each code element is also determined accordingly. The phase difference of the "0" and "1" digital carriers is fixed to 180°, so 0 and 1 can be simply used to represent the two carrier phases. In the phase detection module, the code length divider is used as a 1-bit delayed clock signal. The input digital signal delays one code element signal D-1 and is compared with the 2-to-1 selector control signal S generated last time to obtain the phase Q-1 at the end of the previous code element. The results are shown in Table 1.

Figure 2 MSK demodulator module

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The demodulation of digital MSK signal is realized by two parts: symbol synchronization and code sequence detection. The pre-divider, "1" code divider and synchronization detection module form the symbol synchronization circuit, and the symbol synchronization is established by detecting the "1" code in the input signal. In the synchronization detection module, the in-phase and inverted codes of the "1" code divider are compared with the input signal at the same time, and are counted by the synchronization code length counter. When the count length is equal to the symbol length, the synchronization signal is output. After entering the symbol synchronization state, under the control of the symbol synchronization signal output by the code length divider, the code sequence detector detects the "1" code (in-phase and inverted code) in the input signal and outputs the demodulated digital sequence. The pre-divider and "1" code divider in the demodulation module can be used together with the modulation module in the half-duplex communication mode to reduce the occupation of on-chip resources of the target device.

In the FPGA module of the MSK modulator/demodulator, the counter, frequency divider and multiplexer can be easily implemented using VHDL programs. The partial VHDL structure description of the symbol sequence detector is as follows:

architecture behav of codesdect is

signal m : integer range 0 to 3;

signal sdata : std_logic_vector(2 downto 0);

begin

cdata<= wavenum;

process(clk,clr)

begin

if clr='1' then m<=0;

elsif clk'event and clk='1' then

case m is

when 0 => if datain = cdata (2) then m<=1; else m <= 0 ; end if;

…

when 2 => if datain = cdata (0) then m<=3; else m <= 0 ; end if;

when others => m <= 0;

end case;

end if;

end process;

process(m)

begin

if m=3 then outputt<='1';

else outputt<='0';

end if;

end process;

end behav;

The digital MSK modulator/demodulator module is implemented on Altera's FPGA: EP2C15AF256C8N. EP2C15 is Altera's second-generation Cyclone device (CycloneⅡ) based on 90nm process. It integrates 14,448 logic units (LE), 240Kb embedded RAM blocks, 26 18×18 multipliers, and 4 phase-locked loops (PLLs) on the chip. It has high-speed differential I/O capabilities and is widely applicable in audio and video multimedia , automotive electronics, communications, and industrial control fields. It is a high-performance and low-cost device. Figure 3 is the timing simulation result of the MSK modulator/demodulator.

Figure 3. MSK modulator/demodulator timing simulation

As can be seen from the figure, the digital baseband modulation signal MODDATA is modulated onto the high-frequency digital carrier through the MSK modulator to form the MSK modulated signal MSKMOD, where the "0" code is 2.5 carrier cycles, the "1" code is 2 carrier cycles, the modulation index is 0.5, and the carrier phase is continuous. MSKDEMOD is the signal after MSK demodulation at the receiving end. Except for the transmission delay, the demodulated signal completely restores the digital baseband modulation signal at the sending end.

3 Conclusion

MSK modulation has the advantages of continuous carrier phase and high bandwidth utilization. In common applications, a dedicated integrated circuit is required to form a modulation/demodulation circuit. Using FPGA to implement MSK modulator/demodulator based on hardware description language can make full use of FPGA on-chip resources, so that data acquisition, measurement, control and transmission are concentrated on a single chip, which is conducive to improving the economy and reliability of the system and has certain application value. The innovation of this article is to propose a design method for digital MSK signals that ensures a modulation index of 0.5 and a continuous carrier phase. The modulation/demodulation module is designed in VHDL language and implemented on FPGA devices.