Design of a new SoPC automatic fingerprint recognition system

At present, there are two main ways to implement automatic fingerprint recognition systems based on FPGA: pure hardware implementation [1] and implementation in a soft core with Nios II as the CPU [2-4]. Although pure hardware implementation is faster, it is difficult to implement due to the complexity of the fingerprint processing algorithm. At the same time, the algorithm accuracy is poor and the design cycle is long. Using the soft core Nios II downloaded to the FPGA as the control module has a flexible design method and has the function of software and hardware programmability in the system, which greatly improves the system speed. However, in this solution, software and hardware processing are performed alternately, involving frequent fingerprint data transmission between software and hardware, which limits the system speed and increases the complexity of the system.

This paper proposes a new structure based on SoPC automatic fingerprint recognition design scheme. It has the following characteristics:

(1) Based on the analysis and optimization of the fingerprint recognition algorithm, the software design and hardware design are separated on the basis of the combination of software and hardware. The image preprocessing part of the fingerprint recognition system that takes a long time is implemented in hardware, while the feature extraction, matching and operation control parts that take less time are implemented in the NiosⅡ soft core. This makes the system structure clear and the processing performance is improved.

(2) Use an SRAM as a cache for intermediate data of fingerprint processing. The preliminary processing of fingerprint images is implemented in hardware, and the intermediate data is cached in SRAM; the post-processing software of fingerprint images reads all data from SRAM into the data memory of NiosⅡ. Such a storage design eliminates the need for large amounts of data flow transmission between software processing and hardware processing, simplifies the data interface between software and hardware, and makes data flow control easier. It also avoids the time consumption caused by frequent data transmission between software and hardware.

(3) Based on the combination of software and hardware processing, the fingerprint processing time is greatly reduced. The preprocessing of a fingerprint image can be completed within 1.5 seconds, and the comparison of a fingerprint image can be completed within 3 seconds.

1 Design ideas

1.1 Fingerprint system structure

From the perspective of the entire fingerprint processing system, the system submodules are carefully divided according to the processing characteristics of each algorithm. Through the analysis of the fingerprint processing algorithm, it is found that the fingerprint preprocessing part uses multiple data loop operations, the amount of calculation is large and single, and the use of hardware implementation significantly reduces the time consumption, so the fingerprint preprocessing part is chosen to be hardware-based as a whole; for the fingerprint matching part, the amount of calculation is relatively small but the algorithm is complex and diverse, and the use of software algorithms is relatively simple and can achieve high accuracy, so the Nios II software algorithm is used to implement it. Another advantage of choosing the overall hardware of the preprocessing part and the overall software of the matching part is that the hardware and software processing does not require frequent data exchange and transmission, saving time while reducing the complexity of the system.

As shown in Figure 1, the system workflow is mainly divided into fingerprint hardware acquisition, fingerprint image hardware preprocessing and fingerprint software matching. SRAM is used as a cache device for fingerprint data, Flash is used as a storage device for fingerprint feature data, and the fingerprint data processing steps are carried out in the direction indicated by the arrow.

1.2 NiosⅡ Software Functions

Nios II is the main control module, coordinating the operation of each submodule of fingerprint processing through the Avalon bus. The pre-processing hardware module is hung on the Avalon bus as a whole because the algorithm steps are executed sequentially in the processing, which is convenient for module control. The feature extraction and matching after fingerprint image pre-processing is implemented using Nios II software. The fingerprint data is stored in the data memory of the program, and each function is called for processing according to the software processing flow. In order to facilitate the observation of debugging results, VGA and LCD displays are hung on Avalon. After each step of the algorithm is completed, the VGA display is called to view the processing results, and the LCD is used to prompt the processing steps.

1.3 Hardware Optimization Technology

In order to solve the timing problems that are prone to occur in multiplication and division in FPGA arithmetic operations, and the general problems that consume a lot of resources, such as floating-point operations, square root algorithms, and inverse tangent algorithms, the following optimizations have been made:

(1) Multiplication and division are performed using the IP core that comes with Quartus. The IP core uses a pipeline structure to reduce the occurrence of timing failures in the system and improve system stability.

(2) All floating-point operations are converted to fixed-point numbers by multiplying them, which can reduce the complexity of the operation and the time consumption;

(3) The square root algorithm is implemented using a non-restoring remainder square root algorithm, which only involves addition, subtraction, and shifting. The processing time is only 1/2 of the input bit width, which can reduce system consumption and processing time.

(4) The inverse tangent operation adopts the CORDIC algorithm, which uses a state machine structure and is implemented through repeated iterations. The algorithm is simple.

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2 System Implementation

2.1 MBF200 Hardware Acquisition Module

MBF200 turns on the automatic detection function to collect the entire fingerprint image. By setting the threshold register THR inside the chip, the chip can adapt to different external environments. Changing the values ​​of the three internal registers PGC, DTR, and DCR can adjust the image clarity and improve the quality of the collected image.

2.2 Implementation of the preprocessing module

Image preprocessing is mainly divided into three parts: fingerprint image smoothing, background separation and filter enhancement. The processing of each hardware module is realized through the hardware processing control state machine. The preprocessed fingerprint data is stored in SRAM, and the connection between SRAM and each hardware module is selected according to the hardware state control. Image smoothing adopts normalization processing, background separation adopts variance method, and filter enhancement adopts directional filter image enhancement algorithm to achieve [5].

2.3 Nios Algorithm Implementation

The main modules of the software algorithm are binarization, thinning, feature extraction and feature matching. The binarization process also includes the filling and deletion algorithms after binarization; the thinning algorithm includes the anti-counterfeiting algorithm after thinning. The binarization algorithm uses the threshold method; the thinning algorithm uses the Hilditch thinning algorithm, and uses the feature extraction algorithm based on 8 neighborhood feature points and the matching algorithm based on the center point.

3 System Implementation

3.1 Fingerprint processing VGA display results

Figure 2(a) is the MBF200 acquisition effect diagram. The lines of the fingerprint image are clear and the contrast with the background area is obvious.

The function of normalization is to make the contrast between black and white points in the image more obvious and change the uniformity of the grayscale of the image. Figure 2(b) shows the normalization of the fingerprint after collection. It can be seen from the figure that the fingerprint ridges are significantly strengthened. Since the background area is small, the background separation step is skipped.

The enhancement algorithm based on the directional map is used, and the processing effect is shown in Figure 2(c). As can be seen from the figure, it has a good connection effect on the ridges of the fingerprint image, and can effectively remove the noise interference in the fingerprint image to make the fingerprint clearer and more realistic.

Binarization is performed on the basis of filtering, including the deletion and filling algorithms after binarization. The processing effect is shown in Figure 2 (d). After binarization, only black and white remain in the image.

Thinning is mainly to remove unnecessary thick line information to facilitate the subsequent extraction of feature points. The thinning process is shown in Figure 2 (e). After thinning, only one pixel is left in the line of the fingerprint image. After thinning, pseudo feature points are removed, and breakpoints and short lines are obviously removed.

3.2 Fingerprint processing performance description

The system's processing time consumption is divided into two parts: hardware preprocessing and software algorithm processing.

The hardware processing includes four parts: fingerprint acquisition block, normalization block, background separation block and enhancement filter block; the software processing includes four parts: binarization, refinement, feature extraction and feature matching. The system processing time consumption is shown in Table 1.

According to the characteristics of fingerprint recognition algorithm, this paper designs a new type of automatic fingerprint recognition system based on SoPC. Through the specific analysis and optimization of fingerprint recognition algorithm, the structure of dividing fingerprint processing into two parts, hardware processing and software processing, is designed. A piece of SRAM is used as the cache of fingerprint processing intermediate data. There is no large data flow transmission between software and hardware, which saves data transmission time. This structure uses the full hardware mode for the time-consuming preprocessing part, which greatly improves the operation speed of the system; the matching algorithm part with less time consumption is completed by NiosⅡ software, which shortens the design cycle and improves the design accuracy. This design structure reduces the complexity of the system, makes the system structure clear, improves the processing performance, and facilitates the optimization of individual processing modules and system upgrades.