Contact IC card interface principle and different implementation methods comparison

IC card (Integrated Circuit Card) is another new type of information tool that appeared after magnetic card. IC card is also called smart card, intelligent card, microcircuit card or microchip card in some countries and regions. It is a card made by embedding a microelectronic chip in a card base that meets ISO 7816 standard; it has been widely used in many fields including finance, transportation, social security, etc.

IC card reader is the bridge between IC card and application system, which is called interface device IFD (Interface Device) in ISO international standard. The CPU in IFD is connected to IC card through an interface circuit and communicates. IC card interface circuit is a crucial part of IC card reader. According to different application systems, different IC card reader chips can be selected, such as parallel communication, half-duplex serial communication and I2C communication.

1. Principle of contact IC card interface technology

The IC card reader must be able to read and write IC cards that comply with ISO7816 standards. The IC card interface circuit is the only channel for IC card to communicate with the CPU in the IFD. To ensure the safety and reliability of communication and data exchange, the electrical signals it generates must meet the following specific requirements.

1.1 Complete the IC card insertion and removal identification operation

The IC card interface circuit has strict timing requirements for the recognition of IC card insertion and withdrawal, that is, card activation and release. If the corresponding requirements are not met, the IC card cannot operate normally; in serious cases, the IC card or IC card reader will be damaged.

(1) Activation process

To start the operation of the card, the interface circuit should activate the circuit in the order shown in Figure 1:

◇ RST is in L state;

◇ Depending on the type of card selected, power up VCC to Class A or Class B. The electrical characteristics of VCC under normal operating conditions are shown in Table 1;

◇ VPP rises to idle state;

◇ The I/O of the interface circuit should be placed in the receiving state;

◇ Provide clock signal to the CLK of IC card (1~5MHz for Class A card, 1~4MHz for Class B card).

As shown in Figure 1, add a clock signal to the CLK of the IC card at time t'a. The I/O line should be placed in high impedance state Z within 200 clock cycles (ta) of the clock signal being added to CLK (ta time is after t'a). After the clock is added to CLK, keep RST in state L for at least 400 cycles (tb) to reset the card (tb is after t'a). At time t'b, RST is placed in state H. The response on I/O should start within 400~40 000 clock cycles (tc) after the rising edge of the signal on RST (tc is after t'b).

Figure 1 IC card activation sequence

When RST is in state H, if the response signal has not started within 40,000 clock cycles, the signal on RST will return to state L, and the IC card interface circuit will release the IC card as shown in Figure 2.

Figure 2 IC card release sequence

(2) Release process

When the information exchange ends or fails (for example, no card response or the card is removed), the interface circuit should release the circuit according to the timing shown in Figure 2:

◇ RST should be set to state L;

◇ CLK should be set to state L (unless the clock has stopped in state L);

◇ VPP should be released (if it has been activated);

◇ I/O should be set to state A (not specifically defined within td time);

◇ VCC should be released.

1.2 Provide stable power to the card through contacts

The IC card interface circuit should be able to provide the IC card with a corresponding stable current within the voltage range specified in Table 1.

Table 1 Electrical characteristics of VCC under normal operating conditions

1.3 Provide a stable clock to the card through the contacts

The IC card interface circuit provides a clock signal to the card. The actual frequency range of the clock signal during the reset response should be within the following range: for Class A cards, the clock should be between 1 and 5 MHz; for Class B cards, the clock should be between 1 and 4 MHz.

After reset, it is determined by the F (clock frequency conversion factor) and D (bit rate adjustment factor) in the received ATR (reset answer) signal.

The duty cycle of the clock signal should be 40% to 60% of the period during stable operation. When the frequency switches from one value to another, care should be taken to ensure that there are no pulses shorter than 40% of the short period.

2 Comparison and analysis of several implementation methods

The IC card reader/writer chip in the IFD is classified according to the communication method with the CPU in the IFD. There are parallel communication, half-duplex serial communication and I2C communication reader/writer chips. Figure 3 is a schematic diagram of the principle of a universal IC card reader/writer based on three different communication methods. This system can operate 6 IC cards at the same time, and each IC card reader/writer chip can drive 2 IC cards. The application system can reasonably select one or more reader/writer chips according to the actual situation.

Figure 3 IC card reader/writer principles based on three different reader/writer chips

2.1 Hardware comparison and analysis of IC card reader/writer chips

(1) CTS56I01 with parallel communication mode

CTS56I01 supports two IC cards that comply with the ISO/IEC7816-3 standard T0 and T1 transmission protocols. It communicates with the CPU in the IFD in parallel; it can detect the insertion and removal of the card and automatically generate activation and release timing. Each channel inside the CTS56I01 has 10 independent interrupt sources, such as send buffer empty, ATR timeout, release detection completed, TS not received, etc. When the internal state of the CTS56I01 changes, an interrupt signal can be generated. The system is connected to the data line of the CTS56I01 through the P0 port, and the address selection uses P2[2:0]. The two interrupt signals are connected to the INT0 of the 89C51 after passing through the OR gate. All operations on the IC card are just read and write operations on the internal registers of the CTS56I01, which is convenient and reliable. CTS56I01 uses LQFP-32 package and occupies only a small space.

(2) WatchCore uses half-duplex serial communication

WatchCore is an IC card reader/writer chip launched by Watchdata to facilitate the communication between various embedded devices and IC cards. The hardware platform uses the ST7261 microcontroller, and the internal mask contains all the programs for Watchdata to read and write IC cards. It supports various smart cards with ISO/IEC 7816 T=0, T=1 asynchronous transmission protocols, supports memory card operations, supports dual card head operations, and uses half-duplex serial communication with the interface CPU. The system uses P1.1 and P1.2 to simulate a serial port to communicate with WatchCore. WatchCore is packaged in SO-20, which occupies a very small space on the PCB board.

(3) TDA8020 with I2C communication mode

TDA8020 is a reader/writer chip produced by Philips that supports two independent IC cards. The CPU in the IFD uses I2C to send commands and read status to TDA8020, and sends and receives data to the IC card through the I/OuC port of TDA8020. It supports IC cards that comply with ISO/IEC7816-3 T=0, T=1 standards, and also supports cards that comply with EMV3.1.1 (Europay, MasterCard, VISA) standards. Other chips that are Pin-to-Pin compatible with it include ST8020 produced by ST. TDA8020 has two address selection pins. The address pins of this system are grounded, and the corresponding addresses of the two IC cards are 0x40 and 0x48 respectively. The clock signal and data signal of I2C are simulated by P1.3 and P1.4 of 89C51 respectively, and the data channel I/OuC of the IC card is connected to P1.5 and P1.6 of 89C51. TDA8020 is also packaged in LQFP-32.

2.2 Software Design of IC Card Reader and Writer Chip

2.2.1 CTS56I01 with parallel communication mode

CST56I01 has only 3 address lines, but has 37 registers inside. 8 of them can be accessed directly, and the other 29 registers must be accessed through the index address register (IAR). The access is divided into two steps: the first step is to write the address of the register to be accessed indirectly into the IAR register; the second step is to read data from the data register (DR) or write data to the DR register to complete the access to the register to be accessed indirectly.

The following C51 subroutine is based on the subroutine in Figure 3 that writes a byte to a register to be accessed indirectly.

#define SN2_IAR XBYTE[0x0000]

#define SN2_DR XBYTE[0x0100]

void WriteByteIndexed(BYTE bIndex, BYTE bData) {

P1.0=0;

SN2_IAR = bIndex;

SN2_DR = bData;

}

2.2.2 WatchCore software design

WatchCore is a UART without hardware, and its serial communication is simulated in real time by software. The communication speed is 9600bps; the communication byte format is 1 start bit, 8 data bits, 1 even parity bit, and 2 stop bits. The TXD and RXD electrical signals are standard CMOS levels and can be directly connected to TTL circuits. The following is the data packet format during communication.

(1) Command Packet

The command packet is the data sent from the CPU in the IC card reader to the WatchCore. Its packet format is as follows:

NAD is the card head selection, NAD=0x00/0x12 is the master card head, NAD=0x13 is the slave card head;

PCB has nothing to do with communication. It is used when CPU card T=1. PCB is usually set to 0x00;

LEN is the byte length of the data (the number of bytes in the DATA segment only);

DATA is the command sent to WactchCore or IC card (the command refers to ISO7816-4 standard);

BCC is the XOR check byte (the XOR sum of all bytes in the 4 segments before the BCC segment).

(2) Data Packet

The data packet is the data returned by WatchCore after receiving the command packet. Its packet format is as follows:

NAD* is the return value after WatchCore swaps the high and low 4 bits of the NAD byte in the command packet. For example, if the command packet sends NAD=0x12, WatchCore returns NAD*=0x21;

The other sections are the same as the command packet.

Communication example (the following data are all expressed in hexadecimal)

Reset the main card

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12 00 05 00 12 00 00 00 05

If there is no card in the main card header, WatchCore returns:

21 00 02 62 00 41

If the main card head has a CPU card with T=0, it may return:

21 00 11 3B 7A 18 00 00 21 08 11 12 13 14 15 16 17 18 90 00 D8

2.2.3 Software Design of TDA8020

The communication between TDA8020 and the CPU in IFD is carried out by I2C bus. Through the I2C interface, the CPU in IFD can send commands to TDA8020 or read the status of TDA8020. TDA8020 has two address selection pins (SAD0 and SAD1). In Figure 3, these two address selection pins are grounded, and the corresponding I2C bus addresses of the two IC cards are 40H and 48H respectively. If there are other I2C bus devices in the system, they can be addressed according to Table 2.

Table 2 I2C address selection table of TDA8020

(1) Format of writing commands to TDA8020

Figure 4 shows the format of the command to write to TDA8020. As shown in Figure 3, the address and byte to be written to card 1 is 40H.

The meaning of each bit of the control byte is listed in Table 3.

Figure 4 Timing of writing commands to TDA8020

Table 3 Meaning of each bit of the command control byte

Table 4 Working clock frequency selection method

(2) Data format for reading the internal status of TDA8020

The format of reading the status from TDA8020 is shown in Figure 5. As shown in Figure 3, the address and byte read for card 1 is 41H.

Figure 5 Timing of reading status from TDA8020

The meaning of each bit in the status byte is listed in Table 5.

Table 5 Meaning of each bit of the status byte

3 Conclusion

The above is a detailed introduction to three IC card reader/writer chips with different interfaces. The biggest difference between these three methods is that they communicate with the CPU in the IFD in different ways, and they all comply with the ISO/IEC7816 standard. However, there are some differences between these three reader/writer chips.

TDA8020 supports both Class A and Class B cards, but WatchCore and SNIPER II CST56I01 only support Class A cards. (Although there is a card type selection bit in the internal register of SNIPER II CST56I01, it only supports Class A cards.)

TDA8020 and SNIPER II CST56I01 have ESD protection up to 6kV, but WatchCore does not have ESD protection function.

TDA8020 can directly support the power supply of the card and has an overcurrent protection function; however, WatchCore and SNIPER II CST56I01 can only be achieved through a power amplifier tube, and have no overcurrent protection function, only an external protection circuit (such as adding a resettable fuse).

In terms of the interface mode, although the I2C bus TDA8020 and the serial port WatchCore are convenient to connect with the CPU in the IC card reader, the general CPU does not have extra serial ports and I2C bus interfaces for these two chips, and generally a general I/O port is used to simulate the serial port and I2C bus interface for communication. Although the parallel communication between SNIPER II CST56I01 and the CPU in the IFD requires more connection lines, its corresponding software is much more convenient.

To sum up, these three IC card reader/writer chips are different. In the process of implementing the application, different reader/writer chips can only be selected according to different resource conditions.

References

1 CTS56I01 Data Sheet REV1.0.2. 2002

2 TDA8020HL Data Sheet. 2002

3 WatchCore User Manual. 2002-05

4 Lu Yongning. IC Card Application System. Nanjing: Southeast University Press, 2000

5 Zhang Yigang, et al. MCS-51 single chip microcomputer application design. Harbin: Harbin Institute of Technology Press, 1997

This article was edited and reprinted by Hainaruili , and the copyright belongs to the original author.