Design of Multi-channel Data Acquisition System Based on CPLD

The data acquisition system is highly versatile and can be widely used in military, industrial production, scientific research and daily life. With the popularization of computers, the application of data acquisition systems in daily life is becoming more and more significant. Due to the cost and manufacturing process of high-speed electronic devices based on DSP chips, as well as the high-density technical content, the price of high-speed data acquisition cards is expensive. Complex programmable logic devices (CPLDs) can integrate a large number of logical functions into a single-chip integrated circuit. With its high clock frequency, small internal delay, fast speed, high efficiency, and flexible composition, it has unparalleled advantages in high-speed data acquisition over single-chip microcomputers and DSPs.

1 Design Ideas
The system consists of three parts: data input unit, data processing unit and data output unit. The data input unit is realized by controlling ADC0809 by the state machine. The input signal can be in various forms, such as voice signal, modulated telephone signal, encoded digital signal, compressed image signal, or the output signal of various sensors. A/D can convert analog signal into digital signal, but it must satisfy Shannon sampling theorem, that is, in order to ensure that all information is not lost, the sampling frequency must be higher than 2 times the highest frequency of the input signal. The digital signal obtained after A/D conversion is input to the CPLD chip; then the CPLD chip processes the digital signal with various digital signal algorithms. The processed digital signal is then output through the digital/analog converter ADC0832.

2 Functions and implementation of each part of the system
2.1 Data input circuit
The data input circuit is mainly implemented by controlling ADC0809 by the state machine. Among them, START is the conversion control signal, which is valid at a high level; ALE is the latch signal of the 3-bit channel selection address (ADDC, ADDB, ADDA) signal, which is valid at a high level; EOC is the conversion status signal (similar to the STATUS of AD574). When the conversion is started about 100 μs, EOC generates a high level to indicate the end of the conversion, and it is always at a low level during the conversion. Once START is valid, the status signal EOC becomes a low level, indicating that it has entered the conversion state. After the conversion is completed, EOC will become a high level. OE is the data output enable signal. When OE is high, it controls the opening of the three-state buffer and outputs the converted 8-bit data result to the data bus. Its working sequence is shown in Figure 1.

Analysis of the working process of ADC0809 shows that it works in 6 states. In state St1, the ALE high level stores the 8 sampling input channel addresses of ADC0809 into the ADC0809 address latch. In state St3, the ADC0809 working state signal EOC needs to be cyclically detected. If it is low, it means that the conversion has not ended. It is still necessary to stay in the St3 state and wait until EOC becomes high to indicate that the conversion is over. When the next clock pulse arrives, it turns to state St4. In state St4, the state machine sends a converted 8-bit data output command to ADC0809. This state cycle can also be used as a data output stable cycle so that reliable data can be locked into the latch in the next state. In state St5, the state machine sends a latch signal (the rising edge of LO-CK) to the CPLD to latch the data output by ADC-0809. Its sampling control state diagram is shown in Figure 2.

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2.2 Data processing circuit
The data processing circuit is implemented by VHDL program. The main function of this circuit is to perform cyclic detection on the external input signal. When k1 is 1, the device is in data acquisition and processing mode. The data processing here is to expand the input digital signal by 2 times or reduce it to 1/2 of the original. Fun is used to select the input mode. When collecting data, you can also choose which channel of ADC0809 the collected data is from and display it on the seven-segment digital display. The principle is shown in Figure 3.

2.3 Data output circuit
The data output circuit is implemented by the digital/analog converter DAC0832. ADC0832 is an 8-bit resolution A/D conversion chip. Its internal power input and reference voltage are reused, so that the analog voltage input of the chip is between 0 and 5 V. The D/A conversion result is output in the form of current. The corresponding analog voltage signal should be obtained, so it is realized through a linear operational amplifier with high input impedance. Its connection is shown in Figure 4.

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3 VHDL description of circuits
Data acquisition control circuits and data processing circuits are designed using the hardware description language VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language). For example, the design of the data acquisition control module is as follows:

VHDL language has a multi-level circuit design description function, which can describe both system-level circuits and gate-level circuits; the description method can use behavioral description, register transfer description or structural description, or a mixed description method of the three. The powerful description ability of VHDL language is also reflected in its rich data types. When using VHDL language to describe hardware circuits, designers do not need to first consider the device to be designed. The advantage of this is that designers can focus on optimizing circuit design without considering other issues. After the design description of the hardware circuit is completed, VHDL language allows the use of a variety of different device structures to implement it.

4 Waveform simulation of the system
In the data processing circuit, when gate='1', the entire device is in data acquisition and processing mode. Different working modes, i.e., fun values, can achieve different data processing. When do is 0, its waveform simulation is shown in Figure 5. From the simulation waveform, it can be seen that the input data is equal to the output data. After passing through the output op amp, the output value is doubled, so that the output data is twice the input data.

In the data processing circuit, when gate='0', the entire device is in the loop detection mode. When the input data exceeds the preset value, an alarm is issued, that is, alm='1'. When no input value is greater than the preset value, a loop detection is performed. The waveform simulation is shown in Figure 6.

5 Conclusion
A multi-channel asynchronous data acquisition system based on CPLD is designed. The state machine is used to control data acquisition in the system, and ADC0832 is used for digital/analog conversion. At the same time, the powerful digital processing function and high-density integration of CPLD are used to reduce the cost of hardware, simplify the circuit design, and increase the flexibility and scalability of the system with software, which has good economic and social benefits.