Microchip Launches Industry's First Terabit-Class Secure Ethernet PHY Family with Port Aggregation

Microchip Launches Industry’s First Terabit-Class Secure Ethernet PHY Family with Port Aggregation to Connect Enterprises and the Cloud

META-DX2+ doubles OEMs’ router and switch system capacity by providing 112G PAM4 connectivity for 800G ports while adding encryption and Class C/D precision timing

Driven by hybrid work and the growth of network geographic distribution, the demand for bandwidth and security of network infrastructure is redefining borderless networks. According to the 650 Group, driven by artificial intelligence/machine learning (AI/ML) applications, the total port bandwidth of 400G (gigabit per second) and 800G will grow at a rate of more than 50% per year. This rapid growth is expanding the transition to 112G PAM4 connectivity, not only in switches and routers for cloud data centers and telecommunications service providers, but also in enterprise Ethernet switching platforms. Microchip Technology Inc. is responding to market demand with its META-DX2 Ethernet PHY (physical layer) product portfolio and launching the new META-DX2+ PHY series. This series of products is the industry's first solution to integrate 1.6T (terabit/second) line speed end-to-end encryption and port aggregation functions, helping enterprise Ethernet switches, security devices, cloud interconnect routers and optical transmission systems transition to 112G PAM4 connectivity while maintaining the most compact size.

“With the introduction of four new META-DX2+ Ethernet PHYs, we are working to drive the industry’s transition to 112G PAM4 connectivity supported by the META-DX retimer and PHY combination,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “Combined with the META-DX2L retimer, Microchip now offers a complete chipset that addresses all connectivity needs from retiming and gearboxing to advanced PHY features. By offering hardware and software pin compatibility, customers can leverage the architectural design in their enterprise, data center and service provider switching and routing systems, with advanced features enabled on demand through a software subscription model, including end-to-end security, multi-rate port aggregation and precision timestamping.”

The META-DX2+ features a configurable 1.6T datapath architecture that outperforms the nearest competitor by 2X in total transmission capacity and a hitless 2:1 protection switch multiplexing mode enabled by its unique ShiftIO capability. Flexible XpandIO port aggregation capabilities optimize router/switch port utilization and support low-rate traffic. In addition, these devices support IEEE 1588 Class C/D Precision Time Protocol (PTP) to enable precise nanosecond timestamping required for 5G and enterprise mission-critical services. Microchip enables developers to expand their designs by offering a range of pin-compatible retimers and advanced PHY product portfolios with encryption options to add MACsec and IPsec on top of a common board design and software development kit (SDK).

Differentiating features of META-DX2+ include:

• Dual 800 GbE, Quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY

• Integrated 1.6T MACsec/IPsec engine that offloads encryption from the packet processor, making it easier for the system to scale to higher bandwidths with end-to-end security

• Saves more than 20% in board costs compared to competing solutions that require two devices to provide the same 1.6T gearbox and hitless 2:1 multiplexing mode

• XpandIO enables low-speed Ethernet clients to be port-aggregated onto higher-speed Ethernet interfaces, optimized for enterprise platforms

• ShiftIO functionality combined with highly configurable integrated crosspoints enables flexible connectivity between external switches, processors and optics

• Variable models of 112G PAM4 SerDes with 48 or 32 long reach (LR) capabilities, with programmability to optimize power and performance.

• Supports Ethernet, OTN, Fibre Channel, and proprietary data rates for AI/ML applications

“As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity become increasingly important,” said Alan Weckel, founder and technology analyst at the 650 Group. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimizing port capacity with port aggregation, and providing the flexibility to connect routing/switching silicon to multi-rate 400G and 800G optics.”

Like the META-DX2L retimers, the new family of META-DX2+ PHYs can be used with Microchip’s PolarFire® FPGAs, ZL30632 high-performance PLLs, oscillators, voltage regulators and other components that have been pre-verified as a system to help accelerate time to production.

Development Tools

Microchip's second-generation Ethernet PHY SDK for the META-DX2 family reduces development costs through field-proven API libraries and firmware. The SDK supports all META-DX2L and META-DX2+ PHY devices in the family. Includes support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extension to enable cross-platform support for META-DX2 PHY in various network operating systems (NOS) that support SAI.

Availability

The META-DX2+ family is expected to sample in Q4 2022. For more information, visit the META-DX2+ page or contact a Microchip sales representative.

META-DX2L Ethernet PHY to be Exhibited at European Optical Communications Conference 2022

Microchip will demonstrate the META-DX2L PHY device, which will begin sampling in the fourth quarter of 2021, in the Optical Networking Forum (OIF) booth at the European Optical Communications Conference (ECOC) in Basel, Switzerland, September 18-22, 2022. Microchip and other OIF members will exhibit in booth 701 at the Basel Congress Center to demonstrate how multi-vendor interoperability will accelerate industry solutions for global networks.

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