1 Why develop 3D packaging?
So far, in the field of IC chips, SoC (system-on-chip) is the most advanced chip; in the field of IC packaging, SiP (system-in-package) is the most advanced package. SiP covers SoC, and SoC simplifies SiP. SiP has many definitions and explanations. One of them is the system-in-3D package of multi-chip stacking, which is a package of two or more interconnected bare chips stacked in the positive direction of the chip. SIP emphasizes that the package contains a certain system function. 3D packaging only emphasizes the stacking of multiple chips in the positive direction of the chip. Today, 3D packaging has developed from chip stacking to package stacking, expanding the connotation of 3D packaging. (1) Mobile phones are the main driving force for accelerating the development of 3D packaging. Mobile phones have developed from low-end (calls and sending and receiving short messages) to high-end (photographing, TV, radio, MP3, color screen, chord vibration, Bluetooth and games, etc.), and require mobile phones to be small in size, light in weight and multi-functional. To this end, high-end mobile phone chips must have strong memory capacity. In 2005, 256Mb code storage and 1Gb data storage were required; in 2006, 1Gb code storage and 2Gb data storage were required, so chip stacking packages (SDPs) were born, such as multi-chip packages (MCPs) and stacked chip size packages (SCSPs); [1] (2) In 2D packaging, a large number of long-distance interconnections are required, which leads to an increase in circuit RC delay. In order to increase signal transmission speed, RC delay must be reduced. The short-distance vertical interconnections of 3D packaging can be used to replace the long-distance interconnections of 2D packaging; (3) Copper interconnects, low-k dielectric layers and CMP have become a standard process in today's CMOS technology. As chip feature sizes enter the nanoscale, the requirements for low-k dielectric layers are getting higher and higher, and it is hoped that pure low-k (k < 2.8) dielectric layers will be used. However, the reality did not match expectations, and ITRS postponed the switch to low-k dielectric layers three times (three nodes). At a seminar hosted by the Sematech Alliance at the end of 2003, participants believed that the research on low-k materials for improving IC interconnects may be close to a practical limit, and more attention should be paid to improving the ability to design and manufacture low-k dielectric layers in the future, which shows the difficulty of implementing SoCs. These are the three reasons for developing 3D packaging. Since then, 3D packaging has flourished like mushrooms after rain.
2 Chip stacking
Mobile phones have become the strongest and fastest growth driver for high-density memory. They are replacing PCs as the technology driver for high-density memory. In 2008, the memory used in mobile phones may exceed that used in PCs. High-density memory used in high-end mobile phones requires small size and large capacity, so chip stacking is inevitable. There are two main types of chip stacking packages, one is MCP and the other is SCSP. MCP covers SCSP, which is an extension of MCP. The chip size of SCSP has stricter regulations than MCP. Usually MCP is a stack of multiple memory chips, while SCSP is a stack of multiple memory and logic device chips.
2.1 Advantages and Disadvantages of Chip Stacking
In March 2004, Sematech predicted that 3D chip stacking technology would fill the gap between the current CMOS technology and new technologies (such as carbon nanotube technology). Chip stacking began mass production in 1998, and most of them were double-chip stacks, as shown in Figure 1. [2] By the end of 2004, ST Microelectronics had launched an MCP stacking 9 chips. The most economical MCP is a stack of 4 to 5 chips. The advantages, disadvantages, prospects and relationships of chip stacking are shown in Table 1, which compares chip stacking with package stacking. [3] Since the chip stacking still maintains its original size in the 2D directions of X and Y, and its height in the Z direction is controlled at about 1mm, it is very popular with mobile phone manufacturers. The main disadvantage of chip stacking is that if one of the chips in the stack fails, the entire chip stack will be scrapped.
2.2 Key technologies of chip stacking
One of the key technologies for chip stacking is wafer thinning technology. Currently, a combination of processes such as grinding, deep reactive ion etching (DRIE) and chemical mechanical polishing (CMP) are generally used. The wafer is usually thinned to less than 50μm. Today, it can be thinned to 10-15μm. To ensure the performance of the circuit and the reliability of the chip, industry insiders believe that the limit of wafer thinning is about 20μM. Table 2 gives the requirements for wafer thinning, that is, the specific control indicators for wafer warpage and unevenness (i.e., roughness).
2.3 Latest Developments in Chip Stacking
By the end of February 2005, the highest level of chip stacking was achieved by Fujitsu and Intel. Fujitsu's memory chip stacked 8 chips, with a chip thickness of 25μm, a chip size of 8mm×12mm, and a chip stacking package height of less than 2.0mm. Intel's memory chip stacked 6 chips, with a chip thickness of 50-75μm, a chip size of 8mm×10mm/8mm×11mm, and a chip stacking package height of less than 1.0mm. In April 2005, ST Microelectronics also launched an MCP stacked with 8 chips, with a chip thickness of 40μm, a "middle layer" thickness between chips of 40μm, and a chip stacking package height of 1.6mm. With this 8-chip stacked memory, the circuit board that used to occupy 1Gb of memory can now accommodate 1GB of memory. [4] ST Microelectronics also launched an ultra-thin narrow pitch dual-chip stacked UFBGA, with a package height of only 0.8mm. Using the BGA process, it is only 1/4 of the normal wafer thickness, and the gold wire ball bonding height is also reduced to 40μm. The company's usual MCP is to stack 2 to 4 different types of memory chips, such as SRAM, flash memory or DRAM. ST Microelectronics launched a 4-chip stacked LFBGA in 2004, with a height of 1.6mm, which will be reduced to 1.2mm in 2005 and 1.0mm in 2006. [5] MCP memory is widely used in mobile phones, digital cameras and portable game consoles in Japan and South Korea. For example, Samsung Electronics provides Sony's portable Play Station game console with a capacity of 64Mb dual-chip stacked MCP, which contains 256Mb NAND flash memory and 256Mb DDR DRAM. It also provides memory MCP for Sony digital cameras, which contains mobile DRAM + NOR flash memory, and mobile DRAM + one NAND flash memory. Overseas, 8-chip stacked MCP for 3G mobile phones has been launched. Its size is 11mm×14mm×1.4mm, and its capacity is 3.2Gb. It contains 2 1Gb NAND flash memories, 2 256Mb NOR flash memories, 2 256Mb mobile DRAMs, 1 128Mb Ut RAM and 1 64Mb Ut RAM. Other companies involved in chip stacking technology include Matrix, Tezzaron and IrVine Sensors. By the end of 2004, Matrix had delivered 1 million 3D-packaged one-time programmable non-volatile memories, using 0.15μm process and TSOP or Multi Media Card packaging, with a density of 64MB. Tezzaron uses 0.18μm process to launch double-chip stacked 3D packaging.
2.4 Interconnection of chip stacks[2]
As shown in Figure 1, the interconnection between chips is completed by gold wire ball bonding, which requires the height of the gold wire ball to be less than 75μm. When multiple chips are stacked, the requirements for gold wire ball bonding are higher, that is, the height of the gold wire ball bonding is required to be lower. IMEC, Fraunhofe-Berlin and Fujitsu have jointly launched the "Chip in Polymer" process, which does not use gold wire ball bonding, but uses direct chip/wafer stacking with silicon vertical interconnection, and the chip is thinned and embedded in a film or polymer matrix, as shown in Figure 2. Its key technologies are: ① Through hole, using DRIE (deep reactive ion etching) to prepare silicon holes, such as using SF6 to quickly etch silicon, and C4F8 can be used to passivate the sidewalls of the through hole during the anisotropic etching process of the multi-process department; ② Through hole filling, using TEOS CVD to deposit SiO2 insulation layer at 300℃, and then depositing TiN/Cu or TaN/Cu; ③ Precise alignment between wafers or chips and wafers, the best alignment accuracy is currently ±1~2μm, which limits the wide application of this technology; ④ Wafer-to-wafer bonding, which can be silicon melt method, polymer bonding method, direct Cu-Cu method or Cu-Sn eutectic bonding method, etc. Wafer-to-wafer stacking technology is suitable for wafers with a large number of chips; chip-to-wafer stacking technology is suitable for wafers with a small number of chips, which requires KGD to be selected first and then bonded to the substrate wafer.
3 Package stacking[3]
Although chip stacking packages integrate more functions, even certain system functions, in an ultra-thin space, the impact of yield and lack of KGD in some ICs require pre-testing of packaged ICs under 3D configuration. To this end, the industry has introduced pre-tested packages stacked in a single solution, namely package stacking, which can be used as an alternative for wireless applications (such as mobile phones, PDAs, etc.). The advantages, disadvantages and prospects of package stacking are shown in Table 1. Package stacking is also called package stacking within a package, and it has two forms (see Figure 3). One is PiP (Package-in-Package Stacking), which is a 3D package that stacks a fully tested internal stacked module (ISM, Inside Stacked Module) on top of a BAP (Basic Assembly Package) to form a single CSP solution. The second is PoP (Pockage-on-Package Stacking), which is a 3D package in the board installation process. Inside it, a fully tested package such as a single-chip FBGA (narrow pitch grid solder ball array) or a stacked chip FBGA is stacked on top of another single-chip FBGA (typical memory chip) or stacked chip FBGA (typical baseband or analog chip). In this way, package stacking can stack chips with mixed integrated circuit technologies from different suppliers, allowing pre-burning and testing before stacking.
At present, IC packaging and testing manufacturers such as Amkor in the United States and STATS Chip PAC in Singapore can mass produce package stacking. Nowadays, CSP package stacking has developed a variety of different forms, as shown in Figure 4. The current wiring restrictions of PCB boards and package adapters are 0.5mm or 0.4mm, which is the minimum practical spacing of CSP packages, so the current popular solder ball spacing of CSP packages is 0.65mm and 0.5mm. Reflow soldering process is required in package stacking. Generally, the thickness of the bottom package mold cover must be less than the height of the top stacked package solder ball bracket. In order to obtain the largest possible bracket height, 65% of the CSP solder ball spacing is selected as the actual solder ball diameter, see Table 3. In reflow soldering, when the flux mask opening size is 1/2 of the CSP solder ball spacing, the height of the bracket after package stacking is shown in the last row of Table 3.
Recently, Amkor has introduced two new CSP package stacks, as shown in Figure 5. The first is similar to the traditional plastic BGA, using 100μm thick chips and ultra-low epoxy wire bonding. The 0.5mm pitch CSP uses a standard 0.3mm solder ball diameter. Assuming a mold cap thickness of 0.27mm and 4 chips are stacked, the total package height after installation on the PCB board is 0.8mm, and a CSP with a solder ball diameter of 0.42mm and a pitch of 0.65mm can be stacked on it. The second is that there is a cavity in the center of the substrate, and the chip is placed in the cavity. Using a 0.2mm thick mold cap, assuming that the thickness of the two chip stacks is 0.2mm, the final total height is 0.65mm, and a CSP with a solder ball diameter of 0.33mm and a pitch of 0.5mm can be stacked on it. The top surface of both packages has copper pads along the mold molding area for another package to be stacked on top, as shown on the right side of Figure 5. Both CSP package stacks have passed the moisture resistance test (MRT) and package reliability test.
4 Smart Stacking
In December 2004, Japanese startup Zycube prepared to use a smart stacking technology to create 3D circuits, started manufacturing in the second half of 2005, and launched commercial products in 2007. This smart stacking technology will use a vertical through-hole filling process to increase the number of connections between chips and allow parallel operations to improve performance. This method can avoid a large number of internal connections in SoC, reduce transmission delays and power consumption, and can also merge Si chips and compound semiconductor chips into a single device. ICs based on Smart-stack technology use KGD chips or wafers, which can be any Si chips or compound semiconductor chips, including processors, memories, sensors, analog ICs and RF chips, which can be stacked and electrically connected through vertical filling internal connections.
At present, major IC manufacturers, universities, research institutes and start-ups around the world are stepping up their research on 3D integration technology and 3D packaging technology, such as RPI, Enhof-Munich, Japan ASET (Association for Super Electronics Technology), Tohoku University, IBM, Infineon, Toshiba, North Carolina Microelectronics Center, MCNC-RDI and Tezzaron, etc. They focus on the stacking, bonding, through-holes and interconnection of wafers and wafers, chips and wafers, and chips and chips. 3D packaging is an inevitable product of the miniaturization and multifunctionalization of portable electronic products such as mobile phones, and it will play a big role in this field.
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