Use of Online Logic Analyzer

1. Add IP CORE ILA for debugging

For the BD design file in the figure above, we now need to master some debugging methods to facilitate debugging and simulation of problems later in the development process.

Step1: Click “+” to add the IP of ila CORE.

Step 2: Double-click to open ILA CORE

Step 3: Double-click to open ILA CORE and configure as follows. When finished, click OK.

General Options settings:

Select Native;

Number of Probes:1

Sample Data Depth:1024

Number of Comparators:1

There are three main parameters that need to be configured: 1. Component Name, the name of the component, 2. Number of Probes, the number of signals that need to be captured, 3. Sample Data Depth, the depth of the captured signal.

Step 4: Make the following connections to the added ILA core:

Probe0 is connected to GPIO_LED;

CLK is connected to FCLK_CLK0;

2. Add IP CORE VIO for debugging

Step1: Add vio IP.

Step 2: Double-click VIO core to modify parameters

General Options settings:

Input Probe Count: 1

Output Probe Count: 3

PROBE_IN PORTS Setting: PROBE_IN0 Bit width: 9

PROBE_OUT PORTS settings:

PROBE_OUT0→ PROBE Width(bit width): 1;

Initial Value: Default value 0X00

PROBE_OUT1→ PROBE Width(bit width): 8;

Initial Value: Default value 0X00

PROBE_OUT2→ PROBE Width(bit width): 8;

Initial Value: Default value 0X00

Step 3: VIO IP connection

VIO IP and math IP connection:

PROBE_IN -> result

PROBE_OUT0 -> sel

PROBE_OUT1 -> ain_vio

PROBE_OUT2 -> bin_vio

VIO IP and ZYNQ IP connection:

CLK-> FCLK_CKL0

Step 4: Connect the overall system circuit.

2.5 AXI4 Add IP CORE ILA

Step 1: Right-click the bus you want to observe, here select the S_AXI interface of math_ip

Step 2: After adding, click Run Conection Automation

You can see that the software automatically adds a System ILA IP CORE (this function is only available in VIVADO2017.1 and above)

2.6 Compile FPGA Project

Step1: Click the Block file → right click → Generate the Output Products → Global → Generate.

Step2: Click the Block file → right click → Create a HDL wrapper (generate HDL top-level file) → Let vivado manager wrapper and

auto-update (automatic update).

Setp3: Click Run Synthesis, if a Save dialog box pops up, select Save.

Step 4: Add constraint files, generate bit files, export hardware, and load SDK.

2.7 Loading into SDK

Step 1: Create a new empty project.

Step 2: Copy the main.c source file of the SDK project in the provided example and paste it into the new SDK project.

Step 3: Right click on the project and select Debug as -> Debug configurations

Step 4: Select system Debugger, double-click to create a system debugger, click Apply, and click Debug.

Note: Do not run the program immediately after entering debug, otherwise you will not be able to observe the triggering of the AXI bus signal.

2.8 Loading the Logic Analyzer Waveform Window

Step 1: Return to the VIVADO interface, click Open Hardware Manager → Open Target -> Auto Connect

Step2: After loading, you can see that hw_ila_1 is used to debug the GPIO waveform, hw_ila_2 is used to debug the AXI4 bus waveform, and hw_vio_1 is used to debug the GPIO waveform.

It is the VIO IP used to test math_ip

2.9 ILA GPIO signal debugging

Step 1: Open the HW_ILA1 window, configure ILA, and set the trigger position to 512

Step 2: Configure the trigger signal. When the conditions are met, the ILA waveform will be triggered.

Click the Run button in Status-hw_ila_1 and the following window will appear.

Step 3: In SDK, click the button. When the program outputs 0X01 to GPIO, the trigger signal is triggered.

Summary: Set the breakpoint first and then trigger it;