Loto practical tips (6) SPI decoding with oscilloscope + logic analyzer

In actual applications, only three wires are needed for communication. In SPI, a serial communication protocol, data is transmitted one bit at a time. This is why the SCLK clock line exists. SCLK provides clock pulses, and SDO completes data transmission based on this pulse. The data output changes through the SDO line at the rising or falling edge of the clock to complete one bit of data transmission. The same principle is used for input. After at least 8 changes in the clock signal (one rising edge and one falling edge), 8 bits of data (one byte of data) can be transmitted. The following is a timing diagram of the SPI communication protocol involved in the project for 16-bit data.

This is an example of my first failed attempt. The corresponding waveform collected using LOTO's USB oscilloscope OSCA02 is shown in the figure below.

The long ground wire causes the signal to have a lot of noise, but the root cause of the failure is that my oscilloscope has only two input channels, so I can only see the correspondence between the main clock and one data channel, and it is far from being able to decode. You can intuitively feel what the actual SPI signal looks like, and there are Easter eggs later.  
   
In an SPI-based device, there is at least one master device. The characteristics of such transmission: Unlike ordinary serial communication, which continuously transmits at least 8 bits of data at a time, SPI allows data to be transmitted one bit at a time, and even allows pauses. When there is no clock jump, the slave device does not collect or transmit data. The master device can control the communication by controlling the SCLK clock line. Because the data input and output lines of SPI are independent, data input and output can be completed at the same time. Different SPI devices have different implementation methods, mainly because the time of data change and collection is different, and there are different definitions for collection at the rising or falling edge of the clock signal. The SPI

interface does not require addressing operations and is full-duplex communication, which is simple and efficient. The hardware is slightly more complicated than the I2C system. Since SPI has no specified flow control, there is no response mechanism to confirm whether the data is received.

In my own project, only the data output mode is used, so SPI can communicate in serial 3-wire mode: a clock line SCLK, an output control line CS, and a data output line SDO;

In order to exchange data with peripherals, the output serial synchronous clock polarity and phase of the SPI module can be configured, and the clock polarity (CPOL) has no significant impact on the transmission protocol. If CPOL=0, the idle state of the serial synchronous clock is low; if CPOL=1, the idle state of the serial synchronous clock is high. The clock phase (CPHA) can be configured to select one of two different transmission protocols for data transmission. If CPHA=0, data is sampled at the first transition edge (rising or falling) of the serial synchronous clock; if CPHA=1, data is sampled at the second transition edge (rising or falling) of the serial synchronous clock. The clock phase and polarity of the SPI master module and the external device communicating with it should be consistent.

When the master device configures the SPI interface clock, it is necessary to clarify the clock requirements of the slave device, because the clock polarity and phase of the master device are based on the slave device. Therefore, in the configuration of the clock polarity, it is necessary to clarify whether the slave device receives data on the rising or falling edge of the clock, and outputs data on the falling or rising edge of the clock.
Now, my oscilloscope has been upgraded to OSCA02L, which is an oscilloscope plus a logic analyzer. So this time I have the opportunity to measure 4-wire SPI and decode.