Review and Research on Testing Methods of RAM in Single Chip Microcomputer Systems

In various single-chip microcomputer application systems, the normality of the memory is directly related to the normal operation of the system. In order to improve the reliability of the system, it is necessary to test the reliability of the system. Through testing, the damage caused by memory failure to the system can be effectively discovered and solved. This article specifically introduces several commonly used single-chip microcomputer system RAM testing methods, and on this basis, proposes a RAM fault testing method based on seed and bit-by-bit inversion.

1 RAM test method review

(1) Method 1

The reference document gives a method for testing the system RAM. This method is to check in two steps, first input #00H and then #FFH into the entire data area, then read them out and compare them. If they are different, it means an error.

(2) Method 2

Method 1 cannot completely detect RAM errors. A standard algorithm for RAM detection, MARCH-G, is analyzed and introduced in the reference. The MARCH-G algorithm can provide excellent fault coverage, but the required testing time is very large. The MARCH-G algorithm needs to traverse the entire address space three times. Assuming the address line is the "root", the CPU needs to access the RAM 6×2n times.

(3) Method 3

The reference provides a method to complete the test by shifting the address signal. On the basis of the address signal being all 0, the signal of the address line Ai is only inverted once each time, while the signals of other non-detection address lines Aj (i≠j) are kept at 0, and this is done bit by bit from low to high; then on the basis of the address signal being all 1, the signal of the address line Ai is only inverted once each time, while the signals of other non-detection address lines Aj (i≠j) are kept at 1, and this is also done bit by bit from low to high. Therefore, the shift of the address signal is actually nonlinear addressing according to 2K (K is an integer, and the maximum value is the width of the address bus), and the entire required address range can be regarded as generated by shifting with all 0 and all 1 as the background. Different pseudo-random data is written to the corresponding storage unit at the same time as the address changes. After the above write unit operation is completed, the address signal is shifted in reverse order to read the written pseudo-random data and perform detection. Assuming that there are n address lines, the CPU only accesses 2n+2 storage units in the system RAM.

2 RAM testing method based on seed and bit-by-bit inversion

The test method based on seed and bit-by-bit inversion is further improved on the basis of method 3. Method 3 mainly uses two background numbers of all 0 and all 1 for shift expansion. Compared with the MARCH-G algorithm, the fault coverage obtained is slightly lower, but fewer address units are used. Here we call the background number in method 3 "seed". Taking the RAM with 8 address lines as an example, the seeds are 00000000 and 11111111, 0000llll and llll0000, 00000000, 111111111, 0000llll and llll0000, and 00000000, 111111111, 00001111, 11110000, 00110011, 1100llOO, 01010101 and 10101010 for shift expansion test. The fault coverage achieved is different. The improved method with 2 seeds has a lower fault coverage than the MARCH-G algorithm, the improved method with 4 seeds is equivalent to the MARCH-G algorithm, and the improved method with 8 seeds can exceed the effect of the MARCH-G algorithm. Overall, the improved method based on seeds and bit-by-bit inversion can replace the MARCH-G algorithm, but the number of addressing times required is different for different seed numbers. Assuming that there are n address lines, when the number of seeds is 2, the RAM needs to be accessed a total of 4"+4 times, when the number of seeds is 4, the RAM needs to be accessed a total of 8n+8 times, when the number of seeds is 8, the RAM needs to be accessed a total of 16n+16 times, and the MARCH-G algorithm needs to access the RAM a total of 6×2n times. It can be seen that the improved method based on seeds and bit-by-bit inversion has a much lower test time overhead than the MARCH-G algorithm. At the same time, the fault coverage will increase with the increase of the number of seeds. Of course, the test time overhead required for different seed numbers is also different. In actual test applications, the appropriate number of seeds should be selected according to the requirements of test time and test fault coverage to achieve satisfactory results.

Conclusion

This paper introduces the general method of RAM testing in single-chip microcomputer systems, and proposes a RAM fault testing method based on seeds and bit-by-bit inversion. It has the characteristics of short diagnosis time and high fault coverage, so it has high application value.