S3C2440 memory controller and SDRAM

1. A brief introduction to the memory controller in S3C2440

What is the role of a memory controller and what are its characteristics?

How is the memory controller used by the CPU?

How does the CPU address bus connect to the storage chip?

1. Its functions and features are shown in Figure 1. The following is a simple translation:

The S3C2440A memory controller provides the memory control signals required for external memory access.

S3C2440A has the following features:

- Little/Big Endian (software selectable).

-Address space: Each bank has 128Mb (total 1GB/8 banks).

-Except the programmable bus width of BANK0 (16/32 bits), the programmable bus width of all other BANKs has three types (8/16/32 bits).

-Total 8 BANKs:

BANK0 ~ BANK5 are used for ROM, SRAM, etc.

BANK6 ~ BANK7 can be used for ROM, SRAM, SDRAM, etc.

- The starting addresses of 7 banks, BANK0 ~ BANK6, are fixed.

-The starting address and size of BANK7 are programmable.

-The access cycle of each BANK is programmable.

- You can wait through an external wait signal to extend the bus access cycle.

- Support self-refresh and power-down modes under SDRAM.

figure 1

2. There are many on-chip peripherals (such as GPIO, UART, storage devices, etc.) on our JZ2440 development board. How does the CPU operate these peripherals? When the CPU operates non-storage devices, it directly operates the registers inside the CPU; when it operates storage devices (such as NOR FLASH, DM9000, SDRAM, etc.), it first sends a 32-bit ADDR to the memory controller, and then the memory controller sends a chip select signal according to the range of ADDR, then takes out ADDR0~ADDR26 from ADDR and sends it to the selected peripheral and exchanges data with it, and finally returns the processed data to the CPU; From point 1, we know that the memory controller has a total of 8 BANKs, each BANK is 128Mb (2^27), and the distribution of BANKs is shown in Figure 2

figure 2

3. Here we mainly introduce the example of CPU and ROM connection. The connection of other storage chips of CPU is similar (refer to S3C2440 chip manual). From Figures 3, 4 and 5, we can see that the CPU is connected to A0 of 8-bit ROM with A0, A1 is connected to A0 of 16-bit ROM, and A2 is connected to A0 of 32-bit ROM. In 8-bit ROM, one byte occupies one storage unit, and the memory controller can directly access the specific 1 Byte and return it to the CPU; in 16-bit ROM, two bytes occupy one storage unit, and the memory controller takes at least 2 Bytes at a time, and then determines the specific byte according to the value of A0 and returns it to the CPU; in 32-bit ROM, four bytes occupy one storage unit, and the memory controller takes at least 4 Bytes at a time, and then determines the specific byte according to the values ​​of A1 and A0 and returns it to the CPU;

image 3

Figure 4

Figure 5

2. Simple configuration of SDRAM

How big is the SDRAM memory on the JZ2440 and what is its q starting address?

Simple configuration of SDRAM.

1. There are two EM63A165TS-6G (16M x 16 bit) connected to JZ2440, so the total memory is 64MB. From Figure 6, we can see that the second bit of the CPU address bus is connected to A0 of SDRAM (this also matches the third point in the previous text), but why are there only 17 address lines (plus the 0th and 1st) connected to SDRAM? 2^17 is only 128kb. This is actually because SDRAM is a bit special. Its address is divided into row/column address (that is, nSRAS and nSCAS in Figure 6). It takes 2 address signals to access SDRAM once. There are generally 4 L-BANKs in SDRAM. It selects one of the L-BANKs through ADDR24 and ADDR25, and the row and column addresses of L-BANK are selected through ADDR2-ADDR2. When nSRA is valid, the row address is sent through ADDR2-ADDR14; when nSCAS is valid, the column address is sent through ADDR2~ADDR10. In Figure 6, we also know that its chip select pin is nGCS6, and combined with Figure 2, its starting address is 0x30000000. (Refer to "Complete Application Manual for Embedded Linux Development" written by Teacher Wei Dongshan)

Figure 6

2. By looking at the S3C2440 chip manual, we can see that the registers we need to set when configuring SDRAN in the memory controller are: BWSCON, BANKCON67, REFRESH, BANKSIZE, MRSRB67.

From Figure 7, we know that in the BWSCON register we only need to set BWSCON[27:24], because we have connected two 16-bit SDRAMs and generally do not need a wait signal. At the same time, ST6 is set to 0, because BANK7 and BAANK6 are generally set to the same, so BWSCON = 0x22000000;

According to Figure 8, we set BANKCON6 = 0x18001; BANKCON7 = 0x18001, where the SDRAM column address number (SCAN) we use is 9 bits. According to Figure 9, we take Trcd = 20ns, because our tHCLK is 10ns, so here Trcd = 0b00;

Figure 7

Figure 8

Figure 9

Fig.10

In the REFRESH register of FIG11, Trp is taken as 20ns and Trc is taken as 60ns according to FIG9, so REFRESH[21:20]=0b00, REFRESH[19:18]=0b01, and REFRESH[10:0]=1269 is obtained by combining FIG10 and FIG11; therefore, REFRESH = 0x8404F5; according to FIG12, BANKSIZE = 0x0B1;

Fig.11

Fig.12

Through Figure 10 and Figure 13 we set `MRSRB6 = 0x20; MRSRB7 = 0x20;

Fig.13

Below is the code that puts together the registers set above.

void sdram_init(void)

{

BWSCON = 0x22000000;

BANKCON6 = 0x18001;

BANKCON7 = 0x18001;

REFRESH = 0x8404F5;

BANKSIZE = 0x0B1;

MRSRB6 = 0x20;

MRSRB7 = 0x20;

}

The above is just a brief introduction to SDRAM and how to configure it.