VGA driver display and logic analyzer usage

The interface block diagram of Zedboard is as follows:

The modules on the PL side include HDMI, VGA, OLED, etc. The following will introduce in detail the process of driving VGA on Zedboard. The development environment is Vivado 2016.2. Zedboard is a DAC circuit built by a weighted resistor network.

Regarding the driving principle of VGA, please see the timing diagram below:

The program simulates the generation of horizontal and vertical synchronization signals through counters. Here we mainly introduce the development process of Vivado. Create a new project in Vivado and select the development board Zedboard, as shown in the figure:

Add all the modified project codes. Here, we use the Clock Wizard to regenerate the required clocks. The method is similar to that of Quartus. The transplanted project is shown in the figure:

Then execute Run Synthesis, Run Implementa TI on and Generate Bitstream to generate a .Bit file and download it to the FPGA. Here I want to use the online logic analyzer function, so first I need to add (* mark_debug="true" *) before the signal whose waveform I want to view in the code, so that even if the signal is not connected in the project, it will not be optimized away by the compiler. As shown in the figure:

We will be looking at the VGA red, green, and blue signals in the logic analyzer. Select Set Up Debug and add the signals of interest.

Be careful not to make a mistake in the clock domain. After setting it up, we found that there is an additional debug module in the RTL view.

Then execute Open Target in Hardware Manager, connect to the target development board, Program device, and after downloading, the logic analyzer window will automatically appear.

The final display effect is as follows: