Image acquisition system based on FPGA and MV-D1024E camera

Abstract: The working timing and parameters of the MV-D1024E series high frame rate CMOS camera are analyzed, the CAMERA-LINK interface protocol is explained, and the storage and processing mechanism of high-speed data streams are analyzed. The data interface and control of the camera are realized by FPGA, and a flexible USB interface is designed. The PC is used as the parameter input and display interface. A high frame rate image acquisition system from image acquisition to storage and display is designed. The system has good reliability, high integration, low power consumption, and meets the application requirements of image acquisition systems that do not rely on PCs.

1 Introduction

Image acquisition is the basis of digital image processing, image recognition and machine vision, and its application field is very wide. It mainly uses photoelectric conversion devices such as CCD or CMOS to convert optical images into digital signals, and then uses the corresponding interface to input the data into the processor for digital analysis and processing of the image. MV-D1024E is a high frame rate series camera based on CMOS, with CAMERA-LINK interface. CAMERA-LINK is a high-speed data connection protocol for industrial applications, which can provide a simple and flexible communication interface between digital cameras such as CCD or CMOS and image acquisition systems.

Usually, the image acquisition system is based on digital cameras such as CCD or CMOS, and an acquisition card is needed to complete data acquisition. Common acquisition cards are based on DSP and FPGA. The MV-D1024E series camera also has an acquisition card provided by the manufacturer. It receives the data from CAMERA-LINK and is simply processed by the acquisition card. The data is transmitted to the PC through the PCI bus. However, this type of data acquisition method based on the PCI bus has certain defects. The data can only be connected to the PC through the PCI interface, and the image processing function can only be completed by the PC. This makes the system unable to run without the PC. In many image processing applications, it is necessary to be separated from the PC, and the system is required to be small in size, light in weight, low in power consumption and good in portability. With the widespread application of programmable logic devices, field programmable gate arrays (FPGAs) have been widely used in high-speed real-time image acquisition systems due to their advantages of good reliability, high integration, low power consumption and high computing speed. Here, FPGA is used to control the data interface of the MV-D1024E series camera to realize the image acquisition card function separated from the PC. In order to facilitate system and user input, a USB-based PC interface is designed. Through the USB interface, it can also be used in systems without a PC.

2 Image acquisition system structure diagram

The image acquisition system consists of CAMERA-LINK interface, USB communication interface control, camera control and camera data buffer storage control modules. The system block diagram is shown in Figure 1.

The core controller uses Altera's Cyclone series EPlC6Q240C8. The camera's exposure time, frame rate, display window size and other parameters are set through the PC, and the control command is transmitted to the USB interface control module in the FPGA through the USB. The camera control module integrated inside it transmits the control code corresponding to the camera that has been solidified in the ROM inside the FPGA to the CAMERA-LINK module for processing according to the received parameters, and then sends the control code to the camera through the internal serial module. After receiving the control command, the camera starts working, and sends the image data, clock signal, frame rate signal, line rate signal, and data valid signal to the CAMERA-LINK module of the FPGA through the CAMERA-LINK module encapsulated inside it. The high-speed data stream is ping-pong operated through the data buffer storage module in the FPGA, and then the data is transmitted to the PC for display and storage processing.

3. Design of image acquisition system

3.1 Introduction to EP1C6Q240C8

The FPGA main device is Ahera's CVclone series EPC6Q240C8, which has 5,980 logic cells, 120,000 typical gate resources, and 185 programmable I/O ports. The maximum operating clock can reach more than 300MHz, the core power supply voltage is 1.5V, and the I/O buffer power supply voltage is 3.3V. The system configuration is realized through the JTAG interface. The configuration device EPC4 serial ROM used has a capacity of about 4Mbit and can be repeatedly programmed about 50 times. The JTAG interface complies with the IEEE Std. 1149.1 standard.

3.2 Introduction to MV-D1024E Camera and CAMERA-LINK Interface

MV-D1024E is a high-speed and high-dynamic CMOS camera series. It adopts CMOS active pixel technology, has a sampling resolution of 12 bits and a pixel resolution of 1 024×1 024. At this resolution, the frame rate can reach 150 frames/s. The exposure time is adjustable from 10 μs to 0.41 s, and the stepping is 25 ns. It adopts CAMERA-LINK interface and uses serial port to configure the camera. CAMERA-LINK is an extension technology of Channel Link technology for driving flat panel displays of National Semiconductor Corporation of the United States. Its transmission rate is very high, up to 1 Gb/s, and it provides digital data with high resolution and various frame rates. The data output adopts LVDS format, which is fast and has good noise resistance. According to the application requirements, it supports basic (Base), mid-range (Medium), full (Full) and other digital formats. The interface has an open interface protocol and good compatibility. It is suitable for the communication interface between digital cameras such as CCD or CMOS and image acquisition systems. As shown in Figure 2, when FVAL, LVAL and DVAL are all high at the same time, there is data on the data bus at the rising edge of the camera clock PCLK.

3.3 Camera interface and control module design

The MV-D1024E series camera has 12-bit data output, and is equipped with the camera's clock PCLK, frame rate signal FVAL, line rate signal LVAL, and data valid signal DVAL. Figure 3 shows the camera interface module designed and generated using FPGA. This module completes the access of camera data and various clock signals, and integrates a serial interface module to send the user's control signals to the camera. This completes the camera parameter setting function.

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3.4 USB interface design

The USB interface is used to exchange data and instructions between FPGA and PC. USB (Universal Serial Bus) is a universal serial bus with the advantages of high speed, low cost, low power consumption, plug and play, and easy maintenance. It adopts IEEE1394 bus protocol and the maximum bandwidth can reach 480 Mb/s. The CY7C68013 in the EZ-USBFX2 series of devices from Cypress is used. This is a USB interface host controller based on 8051 microcontroller. It integrates USB2.0 transceiver, serial interface engine (SIE) and enhanced 8051 microprocessor, and also includes an 8.5 KB on-chip RAM, a 4 KB FIFO memory and a general purpose programmable interface (GPIF). The 8051 program running in the internal RAM is provided by the fixed external storage device EEPROM, and the interface with the FPGA is shown in Figure 4.

3.5 Data Buffer Storage Control

Figure 5 is a schematic diagram of data buffer storage control. The MV-D1024E is a high-speed and high-dynamic CMOS camera series. The output collected by it generates a high-speed data stream, which must first be buffered and stored before it can be sent to the PC for display through the USB module. The FIFO buffer module is first used, and then the data is processed and controlled through the ping-pong operation, and finally the data is sent to the PC for display through the USB module.

4 PC software design

The PC is mainly used for user input and display of collected data. It is developed through Visual C++6.0 compilation environment, with simple structure and easy implementation. The process is shown in Figure 6. The user sets the camera's resolution, exposure time, window size and other parameters through this interface.

5 Conclusion

The image acquisition system implemented with FPGA completes the data interface and control of the high frame rate CMOS camera. The USB interface integrated with FPGA can use a PC as a simple user input requirement, or it can be completely independent of the PC to establish an image acquisition and processing system independent of the PC.