Design of frequency sweeper based on single chip microcomputer and FPGA

The frequency characteristics of a network include amplitude-frequency characteristics and phase-frequency characteristics. When designing a system, the frequency characteristics of each network have an important impact on the stability, working frequency band, transmission characteristics, etc. of the system. In actual operation, the sweep frequency meter greatly simplifies the measurement operation, improves work efficiency, and achieves the purpose of fast, intuitive, accurate and convenient measurement process. It is widely used in production, scientific research and teaching. This design uses digital frequency synthesis technology to generate sweep frequency signals, with single-chip microcomputer and FPGA as the control core. Through interface circuits such as A/D and D/A converters, the step adjustment of the sweep frequency signal frequency, digital display and display of the amplitude-frequency characteristics and phase-frequency characteristics parameters of the measured network are realized.

1 System overall plan and design block diagram
1.1 System overall plan
Taking the sinusoidal sweep frequency signal source with adjustable output frequency step as the excitation Vi of the measured network, the response of the measured network can be obtained as V0. By measuring the amplitude of each frequency point, the effective value of V0 and Vi can be obtained, and the ratio of the two is the amplitude-frequency response of the point; V0 and Vi are compared and shaped by zero crossing, and then sent to FPGA to measure the phase difference, the phase-frequency characteristics can be obtained.
Assume the excitation signal Vi=x(n)=Acos(ω0n+f), and the steady-state output signal V0=y(n). Using trigonometric identities, the input can be expressed as the sum of two complex exponential functions: , where . For input , the steady-state output of the linear time-invariant system is . According to the linear property, the response v(n) of the input g(n) is: . Similarly, the output v*(n) of the input g*(n) is the complex conjugate of v(n). So the expression of the output y(n) is obtained:

Therefore. The output signal and the input signal are sine waves with the same frequency, with only two differences: 1) The amplitude is weighted , that is, the amplitude function value of the network system at ω=ω0; 2) The phase of the output signal is equivalent to a q(ω0) delay in the input, that is, the phase value of the network system at ω=ω0. The control of the amplitude and phase measurement of this scheme is implemented through FPGA, which can make the measurement results accurate.
1.2 System overall design block diagram
The system obtains the externally set frequency sweep range and frequency step through keyboard scanning, and controls DAC904 by calling the DDS control module to output the frequency sweep signal. Since the signal will be greatly attenuated in the stop band of the network under test, the frequency sweep signal of the network under test is processed by program-controlled amplification, and then the effective value is sampled by AD637 and shaped by LM311. The effective value of the signal is converted by MAXl270 to obtain the digital value of the effective value, and the shaped signal is processed by the phase measurement module to obtain the phase difference value. Two RAMs are written in the FPGA to store the effective value and phase difference value of the measured signal. After completing a frequency sweep, the amplitude-frequency and phase-frequency curves are displayed on the oscilloscope through the waveform display module, and the amplitude and phase difference values ​​of specific frequency points are displayed on the LCD. The system implementation block diagram is shown in Figure 1.

2 Design of system function part
2.1 Generation of frequency sweep signal
Direct digital synthesis (DDFS) signal source. It is a completely digital method: first, the digital quantity of the discrete sample amplitude of a period of sine wave (or other waveform) is pre-stored in ROM or RAM, read out at a certain address increment interval, converted into analog sine wave signal waveforms of different frequencies after D/A conversion, and then filtered out the burrs through low pass to obtain the input signal of the required frequency. According to this principle, DDS can synthesize any waveform, and can accurately control the phase, and the frequency is also very stable. It is quite easy to make using FPGA, and the frequency sweep step is simple to implement. Assume that the frequency of the reference frequency source inside the FPGA is fclk, and a phase accumulator with a counting capacity of 2N (N is the number of bits of the phase accumulator), and the frequency control word is M, then the frequency of the output signal of the DDS system is fout=fclk／2N×M. The frequency resolution is: △f=fclk／2N. [page]

If the crystal frequency is 40 MHz, the frequency control word is 24 bits, and the phase accumulator is 31 bits, the output frequency range is 0.02 Hz to 312 kHz, and the step frequency is 40 MHz/231≈0.02 Hz.
The system uses a high-speed 14-bit current output D/A converter DAC904 to make a DDS sweep signal source. The FPGA is used to give it a 20 MHz clock signal to output a 10 Hz to 100 kHz sweep signal. The PCB board made of this device takes grounding into consideration well, so that the output signal can be achieved without obvious distortion at a frequency of 1 MHz. DAC904 uses an internal reference and bipolar connection method, and the output signal amplitude range is 0 to 5 V. Its schematic diagram is shown in Figure 2.

2.2 Amplitude-frequency characteristic test scheme
Use the integrated true RMS converter AD637 to first detect the effective value of each frequency point of the signal, and then read the obtained data into the single-chip microcomputer for processing after A/D sampling. The device has a simple external circuit and a wide working frequency band. It can be cascaded with the A/D converter to sample the effective value, average value, mean square value, and absolute value of any complex waveform. The measurement error is less than ±(0.2% reading + 0.5 mV), which can achieve high measurement accuracy.
2.3 Phase-frequency characteristic test scheme
The counting method is used to measure the phase. The idea of ​​the counting method is to convert the phase quantity into a digital pulse quantity, and then measure the digital pulse to obtain the phase difference. Perform an XOR operation on the converted digital pulse quantity to generate another square wave with a pulse width of T0 and a period of T. If the high-frequency counting clock pulse period is TCP, the count value within a period of T is:

where φx is the degree of phase difference.
This method is widely used, has high accuracy, simple circuit form, and is suitable for FPGA implementation.
In actual measurement, when the frequencies of the two input signals are high and the phase difference is small, the pulses obtained are very narrow, which will cause large errors. In order to overcome the above defects, the idea of ​​equal-precision measurement is introduced (as shown in Figure 3), and the multi-cycle synchronous counting method is adopted. A trigger is used to generate a gate signal with a width that is an integer multiple of the measured signal fa. Counter 1 is used to measure the number N1 of high-frequency pulses fm passing through the gate signal, and counter 2 is used to measure the number N2 of pulses after the gate signal, XOR signal, and high-frequency pulse are ANDed in the same time. Therefore, the phase difference is △φ=N2／N1x36 0°. While measuring the phase, a D flip-flop is introduced inside the FPGA, and one square wave signal is used to control another square wave. The high and low outputs of the flip-flop are used to determine whether the signal phase difference range is greater than 180° or less than 180°.

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2.4 System display circuit design
In order to display the curve on the oscilloscope, it is necessary to send the scanning signal and data signal to the X and Y axes synchronously through two D/A converters. The DA converter in the X-axis direction outputs a scanning signal of 0~5 V sawtooth wave signal, and the data signal is -5~5 V, which reflects the signal amplitude and phase at each frequency point, and is output to the Y-axis direction by another D/A converter.

3 System software design
The system software design consists of a single-chip microcomputer and FPGA. The entire system uses the user key interrupt as the main line, calls different processing functions, and exchanges data with each control module in the FPGA through the bus, realizing the function of measuring the frequency characteristics of the system. The software flow chart is shown in Figure 4.

4 Conclusion
This frequency sweeper uses digital frequency synthesis technology (DDS) to generate a sweep signal. The 14-bit D/A converter DAC904 generates a 10 Hz to 100 kHz sine sweep signal and acts on the network under test. The output signal of the network passes through the effective value sampling circuit and the phase measurement circuit implemented by the comparator LM311 and the FPGA to complete the measurement of the frequency characteristics of the network under test.
In order to test the performance of the system, a resistor-capacitor double-T network with a center frequency of 5 kHz and a bandwidth of ±50 Hz was made. The test results show that in the passband and stopband of the network, the phase-frequency characteristic measurement has achieved a measurement accuracy of less than 3°, and the measurement error of the amplitude-frequency characteristic is less than 50%. In addition, the system can input the sweep range through the keyboard, display the amplitude-frequency and phase-frequency curves through the oscilloscope, and display the amplitude and phase characteristic values ​​of the network at a specific frequency point on the LCD. The system is simple to operate, low cost, accurate in measurement, and has strong practicality.