Research technology on radio frequency interference on UART communication ports

Customers have reported that RF interference centered around 840 MHz is affecting a serial communications port configured as a UART, an interface between a modem containing an AD6903 (LeMans LCR+) digital baseband processor and a host processor.

The problem that arises is the presence of noise in the UARTRX signal connected to the AD6903GPIO_1 pin, and whenever a radio frequency (RF) interferer is present, the signal average voltage moves away from its expected value. The magnitude of the shift in the average voltage depends on the power and frequency of the RF source.

Figure 1 shows how the UARTRX signal going to the GPIO_1 pin of the AD6903 is affected when the RF power amplifier is turned on. In Figure 1, UARTRX going to the AD6903 is shown in pink, the UARTTX signal from the host processor is shown in purple, the power amplifier enable is shown in yellow, and the AD6903 VEXT supply is shown in green.

Figure 1: RF interference on a UART communication port.

When the power amplifier is turned on (yellow), the UART data transmission from the host processor's TX pin to the AD6903's RX pin (pink) fails because the RX signal rises to the middle between high and low levels, which is inconsistent with the TX signal (purple). During the second pulse, when the power amplifier is turned on, the host processor's TX pin and the AD6903's RX pin should both remain high; however, there is noise on the TX pin and the RX signal falls to the middle of its high and low levels. Also note that the noise on the VEXT supply voltage (green) increases and its value increases slightly when the power amplifier is turned on.

However, the problem must be with the PA enable signal and the PA of the same modem, because RF energy from other nearby phones or signal generators can also affect the UARTRX signal going into the AD6903. Using a signal generator sweep to check RF interference susceptibility found that the worst area was about 840MHz, and better at high frequencies and lower.

The series resistor for this signal between the host processor and the AD6903 is used to reduce the logic high level from 3.3V to 2.8V. The nominal resistance of this resistor is 10kΩ. It can be replaced with a smaller resistor, including a 0Ω resistor, because lowering the resistance value will reduce noise, but this will not solve the problem unless a short is used instead.

This problem is not unique to AD6903. Chips from other manufacturers also have similar phenomena. For example, the same problem occurs on pin 37 of SN74AVCA16425GR. Please refer to Figure 2 for its functional block diagram.

Figure 2: SN74AVCA16425GR functional block diagram.

Here 1DIR, 2DIR are high level, OE is low level, so the operation is from port A to port B, and pin 37 (1A7) will receive data from another chipset. This means it is an input type.

In the presence of RF interference nearby, the signal on pin 37 of the SN74AVCA16425GR was tested by making a call with a mobile phone near the test point (within 5 meters). Figure 3 shows that when the device is not powered (I/O state unknown), its output is abnormal; while Figure 5 shows the abnormal output when the device is powered (input state).

Figure 3: Low level goes high.

Interference Principle

This "RF interference pickup" behavior of the UARTRX signal entering the AD6903 occurs centered on a specific RF frequency, and these signal traces are not completely shielded. This phenomenon can be explained: the printed wires of the motherboard pick up interference because there are parasitic inductance, parasitic resistance and parasitic capacitance on the wires, and the two ends of the wires are connected to high impedance; one side is a 10kΩ resistor and the other side is a CMOS input. The wires on the circuit board act like an antenna with a 1/4 wavelength response.

Figure 4: High level reduced.

In the customer module, when calculating the GPIO1 wire, the module is calculated as 30mm, while the motherboard is about 15mm. So it is not surprising that this line can pick up RF noise and is sensitive to 840MHz. Please refer to Figure 5 for details.

Figure 5: RF interference calculation formula.

According to the above theory, it is recommended to add a capacitor to the signal path to damp the RF interference oscillation. The role of the capacitor is to change the tuning frequency of the antenna and reduce the antenna impedance, thereby reducing the antenna gain. Later, we heard reports that by selecting appropriate capacitance, the noise was reduced to an acceptable level. The
DC offset of this signal can be generated by the diode of any CMOS input-output pin. They are usually called ESD (electrostatic discharge) protection diodes, but when it is configured as an output, they are actually used to control the depletion region of the transistor of the pin; those transistors often do dual purposes, that is, they also serve as ESD protection devices on the pin when configured as an input. So they are indispensable in all CMOS input/output circuit structures. These diodes are forward biased, and when the amplitude of the signal causes the diode voltage drop (about 0.6V) to exceed VEXT in the forward direction, or to be lower than the ground level in the reverse direction, the signal will be clamped. In order to increase the amplitude of the signal with the increase of RF energy in the antenna band, the average voltage of the signal will be close to half of the VEXT voltage.

This explanation tells us that the peak-to-peak value of the signal is from VEXT+0.6V to -0.6V. However, the amplitude measured by the oscilloscope is much smaller. To explain why the amplitude is reduced, we estimate that this is due to the attenuation caused by the oscilloscope probe and contact resistance, or the sampling rate of the digital oscilloscope is not enough. For example, in order to collect a complete signal near 1GHz (especially when the display window is about 10ms), the actual sampling rate may be much slower than the required 2G samples/second. This theory is described in Figure 6.

Figure 6: Illustration of the DC voltage offset observation.

The RF interference signal is picked up by the printed wire and fed into the chip. The standard chip input/output attenuator acts as a rectifier. As part of all CMOS input-output pins (chip input/output), the diode is forward biased and the signal swing is clamped when the forward voltage exceeds the diode tube voltage drop (about 0.6V) VEXT, or when the reverse voltage is below the ground level. At the same time, the oscilloscope and/or probe cannot measure GHz frequencies, and its performance is equivalent to a low-pass filter. As a result, abnormal voltages appear on "some" input/output pins (depending on the printed wires connected to the input/output pins and the design level of EMC).

There are also reports that replacing the 10kΩ series resistors with 0Ω resistors does not eliminate interference or DC level offsets, but replacing them with short wires does. Paying attention to those resistors can explain that even 0Ω resistors will produce parasitic inductance due to the package being connected in series with a certain amount of resistance. When considering high frequencies, this series RL component acts more like a low-pass filter than a pure resistor. Therefore, it seems that the resistance component may still have considerable impedance in the RF band where interference occurs.

solution

There are two ways to reduce/eliminate the above effects:
1. Eliminate/reduce the "interference source" and increase the system interference immunity (EMC protection) capability, such as isolating the RF circuit from other digital circuits, adding independent RF and baseband shielding areas, maintaining good grounding, and using EMC materials in the mobile phone casing.
2. In order to remove this "interference", a small capacitor should usually be used (note that the capacitor should be close to the I/O pin). By adding a 27pf capacitor to the ground near the (AD6903.GPIO1) (UART_Rx) test point. From the oscilloscope measurement, it can be found that the input/output DC offset is eliminated. And the corresponding bit error rate of the UART communication port is normal. Refer to Figures 7 and 8 for details.

Figure 7: Low-level normal trace.

Figure 8: High level normal trace.