VHDL Design Simulation and Testing of Bus Control Logic

　　A computer system is made up of many modules with independent functions connected to each other. With the continuous development and widespread application of computers, manufacturers not only provide users with complete systems, but also design and provide plug-in modules with various functions, allowing users to build their own application systems or expand the original systems according to their needs. These modules need to communicate with each other, and a high-speed and reliable information exchange channel is required, which is the bus. The bus allows the signal lines between the computer modules to be directly connected to each other, which increases the speed of signal transmission.

　　VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) is a hardware description language that is widely used in the field of electronic design. The latest version is the IEEE standard 1076-1993, which was published by IEEE in 1993. VHDL is mainly used to describe the structure, behavior, function and interface of digital systems. This article uses VHDL's finite state machine to describe and simulate the logical behavior of a computer bus controller.

　　1 The bus operates under the control of the bus controller

　　In the process of information communication between modules of a computer system, only one set of information can be transmitted on the bus at any time. If there are multiple sets of information to be transmitted, they can only be transmitted in sequence under the control of the bus controller. In this way, the transmission of each set of information forms a transmission cycle, which includes the application allocation stage, the addressing stage, the data exchange stage and the revocation stage. In the application allocation stage, the master module submits an application for bus use, and obtains the right to use the bus after approval by the bus controller; then the master module places the address of the slave module on the address bus, which is the addressing stage; after receiving the address, the slave module makes corresponding communication preparations, establishes communication with the master module, and exchanges data; after the data exchange is completed, the master module notifies the bus controller and returns the right to use the bus, which is the revocation stage. There are two commonly used bus communication methods: synchronous communication method and asynchronous communication method.

　　2 Finite state machine description and simulation of synchronous communication mode

　　In synchronous communication mode, the communication transmission cycle between modules is fixed. There is an accurate and stable system clock as the "ruler" of the transmission cycle. Both parties in communication strictly follow the clock ruler to perform various operations. For example, the master module (such as CPU) reads data from the slave module (such as memory). The block diagram of the bus controller is shown in Figure 1.

　　The control state transition diagram of the bus in this way is shown in Figure 2.

　　Describe it with VHDL and simulate it on MAX+PLUSII. The result is shown in Figure 3:

　　As can be seen from Figure 3, the controller is initially in state 0 (idle state), at which point the bus approval control signal grant, the chip select signal csbar, the address validity signal effect, and the read control signal rbar are all at an invalid high level; once a master module issues a bus request, that is, the request signal is at a low level, the controller transfers to state 1, the bus approval control signal is valid, and the application is approved. It is assumed here that there is only one master module, that is, there is no situation where multiple master modules compete for the use of the bus; after entering state 2, the master module issues an address, here assuming that the address is "AD", and sets the chip select signal csbar and the address validity signal at the same time. The effective signal effect is in the effective state. After receiving the address effective signal and the chip select signal from the module, the data preparation is carried out according to the address sent by the master module. After entering state 3, the master module sends a read control signal, that is, the rbar signal is set to the effective state. After entering state 4, it is assumed that the slave module data is ready and sent to the data bus. Here, it is assumed that the data is "DA", and the master module reads the data. After entering state 5, the master module has finished reading the data and sends a withdrawal signal, that is, the withdraw signal is set to the effective state, and then returns to state 0, and all control signals return to the invalid state. At this point, a data transmission cycle ends. During the transmission process, the actions of each module are strictly synchronized according to the system clock.

　　This design is downloaded to the GW48-GK2/PK2 EDA experimental development system. The target chip of this system is EP1K100QC208-3. The hardware test is carried out according to the structure diagram No.0. The experimental system provides restrictions on the test pins and only tests the case where both the address and data are 4 bits (testing the lower 4 bits). The results are shown in Figure 4.

　　As can be seen from Figure 4, in state 0, first set withdraw, request and rst to "1", corresponding to the three light-emitting diodes at the bottom of the figure. At this time, the four output control signals rbar, effect, csbar and grant are "1". These four signals form a 4-bit binary data in order. After being decoded by the decoder, the output result is displayed by the digital tube. Since all four signals are "1", the result "F" should be displayed, as shown in the figure. The upper digital tube displays "F" (the third digital tube on the right). Step 2, set the rst and request signals according to the timing shown in Figure 3 and input a clock pulse by key 3 to enter state 1. At this time, the grant signal is "0", and the four output control signals are combined into "1110". It can be seen that the digital tube in the figure displays "E", indicating that the main module's application for the bus is approved. Step 3, set the address signal addr1 (low 4 bits) to "1010", that is, "A", as shown by the two light-emitting diodes below the digital tube in the figure, and input a clock pulse to enter state 2. The address signal is decoded by addr2 and displayed by the digital tube. As shown in the figure, the rightmost digital tube above displays "A". In this state, the address valid signal effect and the chip select signal csbar are both "0". In this state, the main module sends out the address valid signal and the chip select signal, and the four output control signals are combined to "1000". From the figure, it can be seen that the digital tube displays the number "8". Step 4, input a clock pulse to enter state 3. In this state, the main module sends out a read control signal, that is, set the rbar signal to "0", and all four output control signals are "0", as shown in the figure. The digital tube displays "0". Step 5, set the data signal get_data (lower 4 bits) to "1101", i.e. "D", as shown by the two LEDs below the digital tube in the figure, and input a clock pulse to enter state 4. The data signal is decoded by the decoder and displayed by the digital tube, as shown by the second digital tube on the right above in the figure showing "d". Step 6, input a clock pulse to enter state 5. The main module has finished reading the data and sends a cancel signal, and one data transmission cycle ends; if another clock pulse is input, it returns to state 0.