Automobile anti-collision high-speed data acquisition system based on DSP and FPGA

With the improvement of people's living standards, the number of private vehicles on the road has also increased, but the problem that comes with it is that the incidence of traffic accidents remains high, which seriously endangers people's lives and safety. In this paper, how to prevent traffic accidents, a car anti-theft alarm device with rapid response, high reliability and economical and practical is studied and designed. The key task of the device in the design process is to use the dual-channel channels placed on the left and right ends of the car's front to collect the laser radar echo signal at high speed and store and process it in real time, and then quickly measure the distance and relative speed between the vehicle and the obstacle.

1 System Overview
For radar systems used in highways, considering that the speed of driving is relatively fast, it is impossible to respond immediately to some emergencies. Therefore, the detection distance of the designed anti-collision radar is required to be as long as possible, so that the driver can make safety preparations in advance. Therefore, this kind of highway anti-collision system generally uses laser detection method. The structure diagram of the car anti-collision system using laser ranging is shown in Figure 1.

2 Overall hardware design principle and block diagram
For the electrical signal formed by the laser radar echo signal after conversion by the photoelectric device, its signal frequency is high, the pulse width is relatively narrow, the signal amplitude is low, and the background noise is large. If a low-speed data acquisition system is used for data acquisition, then there will be a lack of data accuracy, so a high sampling rate and high-resolution data acquisition system must be used. The overall principle block diagram of the system is shown in Figure 2.

The main signal flow of the system: The two laser radar echo signals obtained by the laser sensor are first conditioned by the front end such as buffer amplification, and then sent to the AD conversion circuit for analog-to-digital conversion. Then they can be collected by the central logic control module FPGA at the same time, which greatly improves the speed compared with the time-sharing acquisition using DSP. On the one hand, FPGA completes the sampling control of A/D, and on the other hand, it forms a transmission channel with the EMIF interface of DSP, completing the data transmission task between AD and DSP, avoiding direct communication between ADC and DSP, and reducing the pressure on large amounts of data transmission.
2.1 Front-end signal conditioning circuit
2.1.1 Front-end amplifier circuit
The signal output from the sensor must be conditioned before data acquisition can be effectively performed. In order to achieve the highest measurement accuracy, the voltage variation range of the measured signal should be amplified to the vicinity of the maximum range of ADC, so the small signal from the sensor needs to be linearly amplified into an electrical signal suitable for the system through the front-end amplifier circuit. In this system, the low-cost AD8062 operational amplifier module produced by AD Company is mainly used to achieve this, as shown in Figure 3.

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2.1.2 Front-end differential circuit
In order to eliminate even-order harmonic components, suppress common-mode noise sources, and achieve the anti-interference effect of the system, the AD conversion circuit of this system adopts the form of differential input, and the signal is obtained after passing through the amplification circuit. The single-ended signal is converted into a differential signal. This design uses the AD8620 driver chip produced by ADI to form a differential drive circuit. The specific circuit design is shown in Figure 4.

2.2 AD conversion circuit
AD is a relatively important link in the data acquisition system. It mainly completes the acquisition of laser echo signals, and the sampling clock signal can be provided by the clock module inside the FPGA circuit. ADI's AD9481 can use differential input, the sampling rate reaches 250 MSPS, and uses a 250 M PECL standard clock signal. Therefore, in the design, to generate the differential clock signal, consider using the MC100LEL16 clock chip. The digital output of AD9481 belongs to a parallel interface with a 16-bit data stream. For such high-speed data and storage, there will be competition risks, making the system unstable. Therefore, a 100 Ω resistor is connected in series between the AD and the output end of the FPGA during design, which can eliminate the interference between the burrs between 0 and 1 and the high-speed data line. The specific AD hardware principle is shown in Figure 5.

2.3 Data processing hardware circuit
The data processing part of this system is completed by FPGA and DSP. VHDL programming is performed according to the signal output timing of the previous AD circuit to realize the acquisition of digital signals output by two ADs at the same time, input the data into the FIFO module, and then quickly transmit the data to the DSP through the EMIF bus for related algorithm calculation.
2.3.1 FPGA circuit
FPGA uses hardware programming to realize complex logic functions. It can not only pre-process the large batch of collected data streams, but also, as the core part of the entire control system, provide the clock signal required by the system to ensure the orderly collection of data, and as a link for data transmission, it ensures the data transmission between AD and DSP. Combined with sampling, storage, transmission and other functions, the FPGA module is mainly divided into 4 parts: clock management module, A/D control module, FIFO cache module, and EMIF interface module with DSP:
1) Clock management module, this part mainly generates the clock signal of each module required by the system. This system uses the DCM module provided by ISE software to achieve this.
2) A/D controller: Provides corresponding control signals to A/D according to the currently selected sampling mode to make A/D work normally; and collects the digital signal output by AD through the signal output timing of the AD circuit.
3) FIFO cache module: Mainly realizes caching the high-speed collected data into FIFO. When the cache is full, the full flag of FIFO (full) requests an interrupt to DSP. After the corresponding interrupt, DSP uses DMA transmission to read the sampled data into the memory for real-time data processing.
4) EMIF interface module with DSP: DSP is connected to the RAM inside FPGA through EMIF interface, realizing the function of high-speed transmission of cached data in FPGA and DSP.
2.3.2 Interface design between DSP and FPGA
In the design of this system, DSP mainly communicates data with FPGA through the external memory interface EMIF of C6713 device. External memory interface (EMIF) is an interface on TMS DSP device. Generally speaking, EMIF can realize the connection between DSP and different types of memory (SRAM, Flash RAM, DDR-RAM, etc.). Use EMIF to connect to FPGA, so that the FPGA platform acts as a co-processor, high-speed data processor or high-speed data transmission interface.
The bus interface diagram of its EMIF is shown in Figure 6.

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After completing the DSP configuration of EMIF, the next step is to implement the FPGA configuration of the EMIF interface to ensure that the data in the FPGA is read into the DSP normally. The connection diagram for configuring the EMIF interface in the FPGA is shown in Figure 7.

This module is the interface module for DSP to communicate with FPGA. Through this module, DSP can transmit control signals to FPGA, and FPGA can also transmit data in FIFO to DSP through this module. CE, WE, RE, OE are the enable signals input by DSP, CLK provides internal clock for FPGA, CLKOUT2 is the output clock of EMIF, which provides clock frequency for communication between DSP and FPGA, DSP_Addr (19:0) is the input address of DSP, and DSP_DataBus (31:0) is the data bus of DSP. FPGA determines whether EMIF is performing read operation or write operation according to the input logic of read enable signal OE and chip select signal CE. When DSP reads data through EMIF, the data in FPGA is input from dpram_data (31:0) and transmitted to DSP by DSP_DataBus (31:0) pin; if writing data, the data transmitted from DSP_DataBus (31:0) is sent to FPGA from dout (31:0).
2.4 Human-computer interaction module
The human-computer interaction module is divided into key circuit and LCD display circuit. Due to space limitations, this article only introduces the LCD circuit. For
the LCD display part, we use a vacuum fluorescent display dot matrix VFD screen, which has the advantage of high brightness. Since the screen we chose is powered by 5 V, the 3.3 V signal line from the DSP needs to be converted to 5 V through 74LVCA245 and then connected to the controller interface of the VFD screen. The LCD controller interface is shown in Figure 8.

3 Software Design
The system software is mainly composed of DSP and FPGA. The DSP consists of the system initialization part; the EMIF module, FLASH module and SDRAM module of the system function module and the human-computer interaction module. The FPGA design consists of the FIFO module and the DCM module. The overall software module block diagram is shown in Figure 9.

In the whole system, the DSP chip is responsible for the DSP system initialization part and the system function module. The DSP system initialization part includes the DSP boot program, the setting of each hardware register in the DSP chip, and the setting of registers such as EDMA and timer interrupt. The system function module includes the FLASH module and the SDRAM module. Since the data capacity that the DSP needs to process in this system is relatively large and its own storage capacity is insufficient, some data needs to be stored in the FLASH. During the operation, a lot of data processing must also be performed in the SDRAM; and the DSP EMIF module is mainly used to connect FPGA, FLASH and SDRAM.
The FPGA logic design part includes AD logic design, DCM logic design and FIFO module logic design. The main purpose of this functional design is to use the hardware logic module of the FPGA to collect 2-way high-speed AD data at the same time, and put the data into the FIFO generated by the IPcore of the ISE software. Finally, the FIFO transmits the data to the DSP through the logic interface corresponding to the EMIF. During the entire logic design process, the clock is generated by the DCM module. The DCM module can be generated by the IPcore of the ISE software. The clock frequency required by the system can be generated through the IP core, which has the advantages of less delay and less jitter.
Finally, the human-computer interaction program mainly includes the LCD module and the keyboard module. The LCD is used to display the data, and the keyboard module is used to set various parameters of the system.

4 Conclusion
Based on the in-depth study of the current development status of high-speed data acquisition systems, FPGA programmable control devices and DSP digital signal processing systems, this paper adopts a high-speed ADC+FPGA+DSP design scheme to design a high-speed data acquisition system that can be used in high-speed car anti-collision alarm equipment to detect the distance between the target car and the obstacle in real time, and promptly remind the driver to be vigilant and pay attention to safe driving.