High-speed signal measurements with pre-emphasis and equalization

1. Challenges of high-speed signal debugging

In high-speed designs with a rate of Gbps, the most common problems are usually poor eye diagrams, excessive jitter, etc. As shown in Figure 1, the eye diagram at the pin of the receiving chip is very poor, and the jitter components are very complex. For such problems, if we use the unique jitter decomposition function of the LeCroy oscilloscope to decompose and analyze the jitter, we can clearly see that the main jitter comes from the 330khz frequency point and the 125MHZ harmonic frequency point (such as 250MHZ, 560MHZ or so). Based on these frequency points, we can more quickly and easily find that the problem of this system may be mainly due to the imperfect design of the power supply part and the 125MZH clock circuit, so that we can improve these circuits in a targeted manner.

When the signal rate is further increased, improving the design circuit alone may not be able to completely improve the signal eye diagram. At this time, the transmitter chip generally has a pre-emphasis adjustment function, but the design engineer needs to adjust the pre-emphasis to the optimal value to ensure the optimal signal eye diagram at the receiver. As shown in Figure 2, when there is no pre-emphasis/de-emphasis, the eye diagram at the transmitter is very good, but the eye diagram at the receiver is very poor; after adding pre-emphasis, the eye diagram at the receiver is effectively improved. Since chip manufacturers generally provide a variety of pre-emphasis levels and amplitude adjustments, engineers usually need to try to choose the best one. The general method is to test the signal at the receiver. Each time the pre-emphasis is adjusted, the signal eye diagram at the receiver is tested. It takes many tests and comparisons to find the optimal value, which is usually inefficient.

When the signal rate is higher, usually reaching above 5Gbps, it is difficult to improve the eye diagram of the receiving end signal by debugging the circuit and adjusting the pre-emphasis of the transmitter chip. As shown in Figure 3, the transmitter has indeed added pre-emphasis, but the eye diagram of the receiver is still closed. It is impossible to analyze the closed eye diagram. The strange thing is that even if the eye diagram is so bad, the system still works well. Why is this? Because the chip receiver uses equalization technology. Although the eye diagram measured at the receiver pin has tended to be closed, the eye diagram after equalization is usually well improved. As shown in the lower right side of Figure 3, the eye diagram after equalization is already very good, but it can be seen from the figure that the point after equalization is inside the chip. The oscilloscope may not be able to directly test the equalized signal, and what we really need to analyze is the equalized eye diagram. Then everyone should ask, if the oscilloscope can no longer measure the equalized signal at the receiver, then what is the use of the oscilloscope? Is it still meaningful to test and analyze the signal at the receiver chip pin? LeCroy Eye Doctor II software can solve these problems for you.

Figure 3 High-speed signal testing with pre-emphasis and equalization

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2. The main steps of typical high-speed signal design

As the current technological level is getting higher and higher, there are more and more signal standards with signal rates higher than 5Gbps, such as PCIE2.0 reaching 5Gbps, and the 8Gbps PCIE3.0 standard may also be launched soon; USB3.0 reaches 5Gbps, SATAIII reaches 6Gbps, etc. The further increase in signal rates also puts forward more stringent requirements for circuit design engineers;

A typical hardware system design process generally includes five steps: overall scheme design: mainly completing the functional block diagram of the system, schematic design: mainly completing the detailed electrical connection diagram of each functional module in the system, PCB design: mainly completing the electrical connection diagram of each functional module in the system, processing the PCB layout into an actual single board without components, and finally soldering the components for debugging and testing of functional signals, as shown in Figure 4.

In the past, in low-speed systems, testing and verification were usually only performed at the last step of the hardware system design process to ensure that basic functional requirements were met. For high-speed systems, the requirements are greatly different. The first difference is that signal quality analysis needs to be performed at an earlier stage of the design. Usually, a strict signal integrity analysis is performed in the third step of the hardware system design process, that is, after the PCB layout design has been completed but before the board is put into use; the second difference is that not only the functional test requirements need to be met, but each high-speed signal also needs a large margin in addition to meeting the requirements to ensure the high reliability of the high-speed signal and even the entire system. For signals above 5Gbps, another difference is that some standards have clearly stated that tolerance testing of the receiving end is required, such as USB3.0, while the receiving end test was only an optional test in the past.

3. Typical high-speed backplane system and its main design and debugging process

Let's take a high-speed backplane system as an example to illustrate the design process of the high-speed system. As shown in Figure 5, a typical high-speed signal transmission system consists of two line cards and a high-speed backplane. We can see that the bottom of the figure is a backplane with a high-speed connector. There are two line cards (line cards) plugged into the backplane on the left and right through the connector. The line card on the left has a high-speed signal sending chip, and the line card on the right has a high-speed signal receiving chip. As shown by the red line in the figure, the high-speed signal is sent from the sending end chip on the left daughter card, and passes through the transmission line on the line card, the connector, the routing on the backplane, the connector, and the transmission line on the line card to reach the chip receiving end. The high-speed signal traces on the daughter card are usually short and have little impact on the signal; the traces on the backplane are relatively long and have the greatest impact on the signal. The backplane area is usually large and the production cost is also high, so for such a system, the success or failure of the backplane design will be crucial; the main challenge of designing such a system is how to effectively solve the impact of the backplane transmission line on the signal quality (such as reflection problems caused by impedance discontinuity, excessive signal amplitude attenuation caused by long traces, ISI problems of high-speed signals, and impedance continuity problems at the connection between boards). Of course, choosing the right chips, connectors, PCB boards, etc. is also a very important factor. Such problems can be better solved by combining simulation methods with test methods.

Make an equivalent model of the high-speed backplane system on the previous page, as shown in Figure 6. Since the lines on the line card are short, we simplify the transmitter and receiver line cards, and represent them as transmitter and receiver. Usually, the transmitter has pre-emphasis and the receiver has equalization. The long transmission line on the backplane is mainly used to transmit signals, which is usually called a channel, that is, a channel for transmitting signals. In SI literature, it is also called interconnection. The S parameter model can be used to equate the response of the channel. The S parameter model can be obtained through VNA testing or simulation software such as electromagnetic field and CAD. [page]

For today's high-speed system design, signal quality control needs to be performed in more design links. For the typical high-speed backplane system mentioned above, there are generally three links: (1) The PCB layout of the daughter card and the backplane has been completed (the daughter card refers to the transmitting terminal card and the receiving terminal card); (2) The daughter card has been processed, and the PCB layout of the backplane has been completed but has not yet been processed; (3) The PCB layout of the daughter card and the backplane has been completed;

For the first link, that is, the PCB layout of the daughter card and backplane has been completed, the software simulation method is mainly used. For example, the HSPICE software is used to integrate the HSPICE model of the transmitter and receiver chips and the S parameter model of the backplane for channel simulation. The advantage of this link is that there are only circuit design drawings at present, and the physical object has not yet been made. If problems are found at this stage, the design can be easily modified and adjusted without causing a lot of cost losses; and it will greatly shorten the product development cycle and save time; the disadvantage is that the chip manufacturer needs to provide an accurate HSPICE model (sometimes it is difficult to obtain such an accurate model); the signal source used by the simulation software is an ideal signal source, and the actual situation on the daughter card such as crosstalk, reflection, etc. is not considered, and the current high-speed simulation software has a relatively slow simulation speed, which will greatly affect the debugging efficiency.

The second link is that the daughter card has been processed, and the PCB layout of the backplane has been completed but not yet processed. At this time, it is necessary to analyze it through simulation and testing. The analysis method is to first use an oscilloscope to analyze the signal quality of the daughter card output. At this time, it is usually necessary to design a simple fixture to facilitate the high-speed signal from the daughter card to the oscilloscope; then use the relevant electromagnetic field or CAD software to extract the S parameter model of the transmission line of the backplane; then try to compile the signal output by the daughter card into a source code format that can be recognized by HSPICE, and bring it into HSPICE for simulation, so as to obtain the signal quality after passing through the backplane, so as to evaluate whether there is a problem with the design of the backplane. This process is also called "channel emulation". The advantage of this link analysis is that the real signal output by the daughter card can be brought into the simulation, which is closer to the actual situation; evaluation before the backplane is produced will also save costs, and the backplane processing will usually be more expensive. The disadvantages are as follows: the sub-card fixture will bring additional influence to the signal itself, and it is not easy to eliminate the influence of the fixture using simulation software; the measured signal needs to be converted into a format that can be recognized by the simulation software, which is more troublesome. If the oscilloscope can directly simulate the channel of the tested signal in the oscilloscope, that is, the oscilloscope has functions similar to simulation software, it will be very convenient; and the current high-speed simulation software has a relatively slow simulation speed, which will greatly affect the debugging efficiency.

The third link is that all boards have been processed; the main analysis method of this link is direct testing, that is, using an oscilloscope to test the signal eye diagram of each point on the transmitter and receiver. The signal eye diagram quality is adjusted by adjusting the chip transmitter pre-emphasis and the receiver equalization. The advantage of this link is that the signal quality is analyzed completely under actual conditions, taking all actual factors into consideration; the disadvantage is that if the chip has pre-emphasis and equalization functions, each adjustment of pre-emphasis and equalization requires a test, which will reduce the test efficiency a lot; and the equalized signal cannot be tested;

In summary, the main problems that may be encountered in high-speed signal testing are:

(1) When a fixture must be used, how to eliminate the influence of the fixture, i.e. fixture de-embedding

(2) When the signal at the transmitting end can be tested, how to simulate and predict the signal quality after passing through a certain transmission line or system (such as a high-speed backplane) is called channel simulation.

(3) If the receiving chip has an equalization function, how can we observe the waveform after equalization?

(4) If the eye diagram at the key part of the receiver chip is closed, how to analyze the eye diagram and jitter

(5) Is there a more efficient way to adjust pre-emphasis and equalization to the optimal value more quickly during the test?

4. LeCroy's latest second-generation Eye Doctor software (EyeDoctorII) provides a comprehensive high-speed signal testing solution

As early as 2006, LeCroy first launched the unique dedicated signal integrity analysis software Eyedoctor software; in 2009, it launched the latest generation of dedicated signal integrity analysis tool software, the second generation Eyedoctor II, which is more convenient, more powerful and faster, as shown in Figure 7.

● Eye Doctor II is a signal integrity analysis software package installed on LeCroy oscilloscopes, which can mainly meet the following applications

Accurately compensate for the effects of fixtures in tests
Simulate the response of serial data link channels
Perform pre-emphasis and equalization adjustments on TX and RX
● Main analysis capabilities include

Fixture/cable/channel de-embedding (De-Embedding)
Transmitter pre-emphasis emulation (Transmitter Emphasis Emulation)
Channel response emulation (Channel Response Emulation)
Receiver equalizer emulation (Receiver Equalizer Emulation)
● Main user analysis interface with flowchart

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● Support adding pre-emphasis or de-emphasis, removing pre-emphasis or de-emphasis

● Can optimize and analyze equalization technologies such as CTLE, FFE, and DFE

● Three channel simulation and fixture de-embedding types

● Main advantages of LeCroy EYEDOCTOR II software

Channel simulation and equalizer simulation are very fast. A waveform of several hundred microseconds can be calculated in a few seconds. It can almost measure and calculate the results in real time.
The input waveform of channel simulation is based on actual measurement, taking into account many actual random factors on the circuit board.
Support more equalizer types-CTLE/FFE/DFE
can support up to 8-channel 16-port channel models, and can analyze the crosstalk between multiple links.
Support high-speed signal analysis up to 12Gbps, which can be used for 10Gbps backplane pre-research and equalization simulation, which is very popular in the telecommunications field. It
can calculate large data volumes up to 512Mpts.
Support high-speed serial signal analysis when non-ideal terminal matching is used.
The analysis results are sufficiently accurate and precise.

V. Conclusion

LeCroy's second-generation Eye Doctor II software provides a full range of simulation and analysis capabilities for the transmitter, channel, and receiver of high-speed serial links, changing the traditional R&D and debugging methods of high-speed serial designs, enhancing the efficiency of debugging and analysis of high-speed signals, and making it more convenient to use. In conjunction with LeCroy's latest Zi series oscilloscopes (with analog bandwidth up to 30GHz), it can achieve channel simulation, equalization simulation, and comprehensive measurement and analysis of the currently popular 10G signals.

References

1. Powerful tool for high-speed serial design - Eye Doctor II, Changjun Zhang, LeCroy Corporation