CDR in Serial Data Testing

In today's GHz-rate serial data testing, eye diagram and jitter testing are the two most important test items. In eye diagram and jitter measurement, the test instrument must recover the reference clock from the signal to be tested and use the clock to synchronize and sample the data. Therefore, the method of recovering the clock will directly affect the eye diagram and jitter test results. Various serial data standards specify the parameters of the clock recovery circuit CDR in jitter measurement. Only by correctly setting the CDR parameters of the test instrument can the measurement results be consistent with the actual performance of the chip receiver.

Figure 1 below shows a system diagram of a serial data link. This architecture is used in serial links such as Fibre Channel, Gigabit Ethernet, and SDH. After the signal sent by the transmitter (TX) is transmitted to the receiver (RX) through the channel, the clock recovery circuit of the RX part of the transceiver chip recovers the clock from the serial data, uses the recovered clock to synchronize the serial data, and performs sampling. Due to various reasons, the serial data signal entering the RX may have large jitter. Ideally (when the loop bandwidth of the phase-locked loop PLL is infinite), the clock output by the PLL of the clock recovery circuit is in phase with the input data signal of the RX, that is, zero jitter. At this time, the RX discrimination circuit (such as the D flip-flop in Figure 1) has the maximum setup time and hold time margin. However, since the loop response of the PLL is a low-pass filter characteristic, it can only eliminate the jitter in the low-frequency band of the serial data and cannot process high-frequency jitter. Therefore, in reality, the eye diagram "seen" by the RX end of the transceiver chip has jitter.

In Figure 1, the parameters of the PLL at the RX end are the determining factors affecting the eye diagram and jitter performance. PLL is a widely used electronic circuit that can be used to obtain a clock of a specific frequency, modulate and demodulate RF signals, and recover the clock of serial data.

Figure 2 shows the system diagram of PLL, which includes three basic parts: phase detector, loop filter, and voltage controlled oscillator (VCO). Please refer to analog circuit books for the working principle of PLL.

In the PLL at the receiving end, the frequency response of the loop consisting of the phase detector, loop filter and VCO is a low-pass filter characteristic. As shown in Figure 3 below, the frequency response of the clock recovery circuit at the receiving end is a low-pass filter, and its transfer function is HL. When the jitter change frequency of the serial data signal is low, that is, from DC to the cut-off frequency of the PLL, the PLL can track the data jump edge in time (that is, lock the phase), and the output clock is in phase with the input data (strictly speaking, the phase difference is a fixed constant), so the jitter is zero. When the jitter of the continuous edge changes too fast (that is, when there is high-frequency jitter), the PLL cannot track the edge change in time, so there is jitter in the output clock and data edges. Therefore, the CDR at the receiving end cannot filter out jitter higher than the cut-off frequency, and its jitter transfer function (Jitter Transfer Function for short JTF) has a high-pass filter characteristic. The CDR at the receiving end is also called the high-pass filter of TIE jitter. As shown in Figure 3, the jitter transfer function HH=1-HL. [page]

In addition to using the PLL as shown in Figure 1 to recover the clock at the transceiver receiving end, another clock recovery method is to use a phase interpolator (PI). PI is used to recover the clock in both FBDIMM and PCI Express, but when using instrument testing, PLL can be used for modeling.

The instruments that test the eye diagram and jitter of high-speed serial data signals all use a phase-locked loop-based clock recovery method. Among them, real-time oscilloscopes mainly use software PLL to recover the reference clock, while sampling oscilloscopes and bit error rate testers use hardware PLL to recover the clock. Real-time oscilloscopes are the most popular and widely used test instruments. This article only introduces the relationship between software CDR and eye diagram testing and jitter testing of real-time oscilloscopes.

As shown in Figure 4 below, this is a reference for the PLL settings in LeCroy's serial data analyzer. By default, the FC Golden PLL is used. This PLL is a first-order phase-locked loop with a loop bandwidth equal to the bit rate divided by 1667. It was first defined in the MJSQ document for Fibre Channel.

As shown in Figure 5 below, a 2.5Gbps signal is measured using a LeCroy oscilloscope. When the PLL bandwidth of the oscilloscope's serial data analysis software is set at 2MHz, 5MHz, 10MHz, and 20MHz, the eye diagram measurement results are shown. The higher the PLL bandwidth, the clearer the eye diagram and the smaller the jitter. The question is, what is the real eye diagram and jitter received by the transceiver RX end of the circuit under test? The answer is that the CDR parameters of the oscilloscope must be set to be exactly the same as the CDR parameters of the RX end of the circuit under test, so that the measurement results of the oscilloscope have reference value.

In Figures 4 and 5, the CDR of the first-order phase-locked loop is used. This type of PLL is used in many serial circuit standards, such as GBE, XAUI, SDH, CPRI, FC, SAS, etc. However, PCIe Gen2, SATA2, and Displayport use the CDR of the second-order phase-locked loop. Figure 6 shows the JTF comparison between the first-order PLL and the second-order PLL. The second-order PLL has a steeper roll-off factor of -40dB/decade (the roll-off factor of the first-order PLL is 20dB/decade). Assuming that the jitter of a certain 500kHz is 150ps (and 500kHz is within the frequency band of the oblique line), the jitter is only 15ps after passing through the first-order PLL, and only 1.5ps after passing through the second-order PLL. It can be seen that for the jitter in the low-frequency band in Figure 6, the second-order PLL can reduce the jitter in this frequency band to a greater extent.

Figure 7 shows the eye diagram measurement results of a 2.5Gbps signal using a first-order PLL or a second-order PLL. It can be seen that the eye diagram obtained using the second-order PLL is very clear and has less jitter. The second-order PLL can reduce low-frequency jitter to a greater extent and is usually used for serial data signals with spread spectrum clocking (SSC), such as SATA and PCIe on computer motherboards. [page]

As shown in Figure 8 below, LeCroy SDA integrates multiple PLL parameter settings such as FC Golden, PCIe Gen1, PCIe Gen2, DVI, FBDIMM, USB3.0 and Custom. When measuring, select the appropriate CDR setting according to the type of signal to be tested.

In summary, correctly setting the oscilloscope's CDR parameters is the key to measuring eye diagrams and jitter. Testers need to refer to the serial data specification or the instrument manufacturer's operating documentation to ensure the accuracy and effectiveness of the measurement.

Reference
1, Fiber Channel – Method Jitter and Signal Quality Specification – MJSQ, T11.2/Project 1315-DT/Rev 14.1, June 5, 2005.
2, Mike Peng Li, "Jitter, Noise, and Signal Integrity at High- speed".