Bit Error Rate Testing Using R Series Intelligent Data Acquisition

Author(s):
Stephen Kulakowski - Harris RF Communications Division

Industry:
Aerospace/Avionics, Telecommunications, RF/Communications, Government/Defense

Products:
Data Acquisition, Digital I/O, LabVIEW, PXI/CompactPCI, FPGA Module

The Challenge:
Replace traditional box-based instruments to support testing of new and existing products.

The Solution:
Develop a more flexible system to test real-world file transfers while reducing unit costs by 1/4 using NI LabVIEW FPGA and R Series intelligent data acquisition.

"Our new system reduces unit costs by 4x and provides the ability to customize the communications interface as our test requirements increase."

Harris RF Communications Division developed the control panel above, which is part of a bit error rate test system that reduces costs by 4 timesHarris

is an international communications and information technology company. We needed to replace the traditional box-type instrument to support the testing of new and existing products. The RF products we test are mainly data transmitters and data receivers, where three different serial interfaces must be verified. Since the old system supports limited communication types, we needed to find an off-the-shelf solution that is flexible and scalable.

Bit Error Rate (BER) Test System

A complete serial bit error rate (BER) test system was implemented using the NI PXI-7833R FPGA module and a wide area network (WAN) transceiver chip on a custom circuit board. The physical interfaces that needed to be verified were RS232, RS422, and RS485, the latter two being balanced interfaces for high-speed applications up to 1.6 Mb/s. The original system only supported 8-bit synchronous and asynchronous communication interface types and was relatively expensive.

The interface to the R Series PXI-7833R module is a custom printed circuit board that uses the Sipex SP514 WAN interface IC for the different physical layer serial interfaces. The board also contains a temperature compensated crystal oscillator (TCXO) and a direct digital synthesis (DDS) circuit to generate a high-speed clock that synchronizes the PXI-7833R data. The 1ppm accurate TCXO can be used as a high-reliability clock source for the unit under test and can also be used for vibration testing and analysis in the future. The data interface interface is based on the EIA-530 communication standard based on a DB-25 port. To improve signal integrity at high speeds, we used coaxial cable for all clock and data lines.

The NI LabVIEW FPGA VI on the target machine contains all the functions of a typical BER test system. The VI accepts all user inputs to configure the timing, physical interface, block size, handshake signals, and synchronization data block size. We also have the option to insert a bit error into the system test. The bit error function randomly flips a bit in the transmitted data pattern to modify the transmitted data. These functions can also be used directly on the host VI, which provides the actual pattern data and completes the test analysis after the data byte is received: reporting BER, bit errors, lost bits, and synchronization.

System Synchronization

To perform multiple synchronizations in a system, the BER tester continuously sends synchronization data of a user-specified size, usually less than 255 bytes. The FPGA code checks and compares the synchronization byte and the stop bit to tell the user or program whether the synchronization is valid. (This is also verified by comparing each specific byte in the pattern transmission.) If it fails and there are significant bit errors, a file is generated for the user to compare the data sent and received by the BER tester. If the synchronization signal is not detected, but the synchronization bit is still available, the object code will use clock shifting methods to try to align the received input data with the synchronization data value. If synchronization is not achieved in the synchronization data block, the test system will report "no synchronization" during the transmission and start the test again.

Basically, each test usually involves two Harris products: one as a data transmitter and the other as a data receiver with appropriate physical interfaces to connect to the BER tester. The system is usually connected by several feet of 50 Ω cable and RF attenuators to ensure high sensitivity and high signal-to-noise ratio between the communication products.

A pre-made random or pseudo-random data pattern is transmitted to the transmitter system under test at a given baud rate; newer BER testers can test at rates up to 1.6 Mb/s. The information is modulated by the transmitting system and sent via RF at a certain carrier frequency. The receiving system receives the RF signal, demodulates it, and transmits it back to the BER test system.

At this point, the BER test system algorithm deterministically compares the received data with the transmitted data and reports the number of error bytes. The transmitted and received data are stored in the target object memory and are then read by the host VI application, which reports the pattern bit errors and calculates the pattern BER. The BER test application algorithm also reports missing bits and synchronization times.

High-Speed ​​Serial Data Processing

To achieve high-speed serial data processing speeds of 1.6 Mb/s, the application needs to be compiled and run on an FPGA clocked at 80 MHz. We need to process data with a data resolution of 20 nS, and in the new system, we can ensure that the target object data processing time is 12.5 nS/bit. This is critical for relatively slow internal memory operations and real-time data comparison. We repeatedly optimized and compiled the target object VI at 80 MHz on multiple test systems. We

implemented deterministic data comparison between LabVIEW FPGA custom memory blocks using direct mode memory comparison. Memory blocks are necessary to improve payload data transfer and comparison; otherwise, only small data blocks can be transferred. Now, users can select to use data modes up to 30 Kb in a drop-down menu.

Calling the target object software from the host VI is a key integration step to support complete ATE product testing. Our current test software architecture uses LabVIEW and NI TestStand.

The test unit can use loopback cables to connect the clock and data input and output to perform self-tests, and can also use SPDT switches to emulate modem handshake signals to verify test procedures. The test results must be zero loss, that is, perfect synchronization, 0 bit loss, and 0 bit errors.

One of the problems we encountered when trying to find an off-the-shelf solution to support the PXI test platform was finding options that could be customized to work with the product communication interface and test. The first instrument option we found did not meet the interface requirements of our product base. With the LabVIEW FPGA test option, we can test the physical layer of multiple serial communications without the need for extensive wiring of boards. The new instrument also provides a lot of added flexibility to test real-time file transfers and images that may be serialized between systems. It is also a PXI-based solution.

Conclusion

The new system reduces the unit cost by about 4 times and provides the ability to customize the communication interface to meet the needs of increased testing.

We are currently investigating ultra-high-speed systems (over 2 Mb/s) using two PXI-7833R reconfigurable FPGA modules.