Speed ​​up design verification with frequency-domain clock jitter analysis

As data rates increase, the need for clock jitter analysis increases. In high-speed serial data links, clock jitter affects data jitter in transmitters, transmission lines, and receivers. Clock quality assurance measurements are also evolving. The emphasis is on establishing a direct correlation between clock performance and system performance in terms of bit error rate. We will review the role of the reference clock and the impact of clock jitter on data jitter, and discuss new measurement techniques used in the Agilent E5001A Precision Clock Jitter Analysis application running on the E5052B Signal Source Analyzer (SSA), which provides outstanding capabilities to measure ultra-low random jitter (RJ) and real-time jitter spectrum analysis of RJ and periodic jitter (PJ) components to improve design quality. We will also discuss the real-time measurement capabilities of this new technology that can accelerate the design verification process.

The Role of Reference Clocks in High-Speed ​​Serial Applications

Figure 1 shows the main components of a reference clock. The transmitter typically serializes a set of low-rate parallel signals into a serial data stream. The transmission channel through which the signals propagate includes backplanes and cables. The receiver interprets the incoming serial data, reconstructs its clock signal, and usually de-serializes it into a parallel data stream. In many descriptions such as this one, the reference clock is considered a component rather than a key player. However, in high-rate serial data systems, the reference clock is used as a key component. Usually the reference clock oscillates at a frequency much lower than the data rate and is then multiplied in the transmitter. The transmitter uses the reference clock to define the timing of logic transitions in the serial data stream. The reference clock is characteristic of the transmitted data. At the receiver, two different situations occur. If the reference clock has not been distributed, the receiver recovers a clock from the data stream, for example, using a phase-locked loop ( PLL ), and uses this clock to locate the sampling point in time. If the reference clock has been distributed, the receiver uses the data signal and the reference clock to locate the sampling point.

Effect of Clock Jitter on Transmitter Data Jitter

The reference clock is the fundamental source of system timing. It provides the time-base of the transmitter. In distributed and non-distributed clock systems, the characteristics of the reference clock are reproduced in the receiver clock recovery circuit. Now, we need to understand how clock jitter propagates in the transmitter of the system.

To define the timing of the logic transitions, the transmitter must multiply the reference clock by an appropriate factor to achieve the data rate. For example, for a 100 MHz reference clock and a 5 Gb/s output signal, the transmitter will use a PLL to increase the reference clock by a factor of 50. The PLL multiplier both amplifies the clock jitter and introduces its own jitter, primarily RJ jitter from the PLL voltage-controlled oscillator ( VCO ). The effect of increasing the frequency by a factor of n is to amplify the phase noise power to carrier ratio by a factor of n2, so jitter increases rapidly.

The PLL multiplier in the transmitter has a finite frequency response, typically on the order of seconds, as shown in Figure 3. The non-uniform frequency response raises an interesting question: What is the effect of clock jitter? If the PLL is good and has zero bandwidth, all clock jitter can be filtered out, providing a jitter-free timebase for the transmitter. Of course, zero bandwidth means infinite lock time, so there is a compromise. But the narrower the PLL bandwidth, the less jitter there is in the reference clock going into the data. To determine if the clock is operating at the desired BER in the system, the jitter spectrum must be carefully measured.

Real World Jitter Sources

There are many sources of jitter in real-world high-speed data circuits, as shown in Figure 4. As mentioned earlier, clock signals are often distributed to multiple ICs, and the clock frequency can be multiplied and/or divided. Assuming that the reference clock from the crystal oscillator has lower jitter, the multiplied or divided output clock will become unclean due to additive noise from the IC or interference from other devices.

A major source of contamination is switching power supply noise with a typical switching frequency of 100 kHz to 1 MHz. This switching power supply noise can enter the clock signal line, which is PJ jitter in the lower left of the figure.

Other sources of periodic jitter components can be interference in the data or clock lines, and inter-modulation products can enter the clock line, which is also considered a component of PJ jitter. As long as the PJ components are far away from the clock frequency, a bandpass filter (or low-pass filter) can be inserted to suppress these jitters. The problem is that when the periodic jitter is close to the clock frequency, high-Q filters are difficult to implement at high frequencies. For RJ jitter of the reference clock, a clock divider circuit will add broadband noise, causing the RJ jitter of the output clock signal to increase.

To diagnose the problem, the clock jitter must be characterized in its actual location in the circuit and/or under operating conditions.

Analyzing the characteristics of clock jitter through phase noise measurement technology

Full analysis of clock signals requires femtosecond (f [fai] second) accuracy, which can only be achieved with phase noise measurement techniques. Phase noise analysis provides two key measurements: S (t), which contain everything from clock phase information to the bandwidth limit of the phase noise measurement. [fai] and RJ jitter analysis with a phase noise analyzer can achieve two important goals. The first is to integrate the RJ power-series characteristics to find the RJ jitter spectrum, that is, to extract the width of the corresponding RJ Gaussian distribution from the desired bandwidth. Second, analyze the main causes of S jitter. (Figure 5) PJ components will be seen as spurs in the phase noise spectrum. Knowledge of the PJ frequency can help diagnose faults. Knowing the PJ rms of each PJ frequency also helps to understand the contribution of each PJ component to the overall clock jitter, so as to examine how much the total jitter will be affected if the main PJ component is removed. (Figure 6)

Real-time jitter measurement with advanced architecture

Unlike conventional jitter measurement examples, the E5052B SSA with E5001A software provides real-time jitter analysis for phase noise measurements. The instrument uses a PLL with reference source. It automatically detects the clock frequency, and the built-in reference source automatically adjusts to the clock frequency within a few milliseconds and measures the noise signal from the phase detector that maintains the PLL. The noise signal captured with a 250 MSa/s ADC supports 100 MHz jitter bandwidth measurement, covering the analysis range of OC-192 jitter. Real-time FFT dynamically acquires frequency domain data, increasing the speed of measurement. For example, it only takes 0.3 seconds to measure a bandwidth from 1 kHz to 100 MHz. Jitter noise benchmark using cross-correlation technology

The E5052B jitter measurements have very low resolution and noise floor, typically femtoseconds of RJ jitter noise floor at 10Gbps. Typical high-performance (real-time or sampling) oscilloscopes have jitter noise floors in excess of hundreds of femtoseconds due to limited dynamic range ADCs and relatively large residual jitter in internal interfering timebases. The E5052B maintains a wide dynamic range by eliminating the phase noise of the fundamental frequency of the larger carrier signal through detection. Even at residual jitter below its internal timebase, the E5052B uses a unique cross-correlation technique between two independent internal measurement channels to extend the jitter measurement limit (Figure 7). Using this cross-correlation technique, the E5052B can achieve jitter noise floors that are 100 to 1,000 times lower than today’s high-performance oscilloscopes (Figure 8).

Simulating PLL response in real time

Figure 9 shows an example of the effect of applying the PLL response function directly to the clock phase noise signal. It can be seen how different parts of the spectrum are suppressed, allowing analysis of application-related jitter. The E5052B's real-time jitter analysis of phase noise measurements accelerates the design process. Any PLL response function can be ported to the E5052B SSA, allowing users to easily and quickly simulate the PLL response from device to device.

Conclusion

For high-speed serial data applications, the main goal of clock jitter analysis is to determine the impact of reference clock jitter on the system bit error rate. The most accurate method is to use the worst-case transmitter (and receiver) transmit function for the application and measure the clock RJ jitter and PJ jitter results. The E5001A Precision Clock Jitter Analysis software running on the E5052B changes the characteristics of traditional jitter measurement products, not only providing comprehensive analysis of clock jitter with femtosecond accuracy, but also providing easy-to-use and real-time jitter analysis capabilities, which will help accelerate the design verification process.

(Author of this article: Akihiko Oginuma, Senior Product Manager, Component Test Division Kobe, Electronic Measurements Group, Agilent Technologies)